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Re: [PATCH v5 57/60] target/riscv: vector slide instructions
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From: |
Richard Henderson |
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Subject: |
Re: [PATCH v5 57/60] target/riscv: vector slide instructions |
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Date: |
Sat, 14 Mar 2020 23:56:32 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 3/14/20 11:49 PM, LIU Zhiwei wrote:
>>> + if (offset > vl) { \
>>> + offset = vl; \
>>> + } \
>> This isn't right.
> That's to process a corner case. As you can see the behavior of vslideup.vx
> from Section 17.4.1
>
> 0 < i < max(vstart, OFFSET) unchanged
> max(vstart, OFFSET) <= i < vl vd[i] = vs2[i-OFFSET] if mask enabled,
> unchanged if not
> vl <= i < VLMAX
> tail elements, vd[i] = 0
>
>
> The spec v0.7.1 or v0.8 does not specified when OFFSET > vl.
Certainly it does, right there:
offset <= i < vl.
If offset >= vl, then that range is empty of elements.
> Should The elements (vl <= i < OFFSET) be seen as tail elements, or
> unchanged?
Tail elements.
> Here (vl <= i < OFFSET) elements are seen as tail elements.
Exactly.
>> Again, eliminate vl == 0 first. In fact, why don't we make that a global
>> request for all of the patches for the next revision.
> I don't get it.
>
> Check vl == 0 first for all patches. Is it right?
Yes.
r~
- Re: [PATCH v5 55/60] target/riscv: integer scalar move instruction, (continued)
[PATCH v5 57/60] target/riscv: vector slide instructions, LIU Zhiwei, 2020/03/12
- Re: [PATCH v5 57/60] target/riscv: vector slide instructions, Richard Henderson, 2020/03/15
- Re: [PATCH v5 57/60] target/riscv: vector slide instructions, LIU Zhiwei, 2020/03/16
- Re: [PATCH v5 57/60] target/riscv: vector slide instructions, Richard Henderson, 2020/03/16
- Re: [PATCH v5 57/60] target/riscv: vector slide instructions, LIU Zhiwei, 2020/03/24
- Re: [PATCH v5 57/60] target/riscv: vector slide instructions, Richard Henderson, 2020/03/24
[PATCH v5 58/60] target/riscv: vector register gather instruction, LIU Zhiwei, 2020/03/12
[PATCH v5 59/60] target/riscv: vector compress instruction, LIU Zhiwei, 2020/03/12
[PATCH v5 60/60] target/riscv: configure and turn on vector extension from command line, LIU Zhiwei, 2020/03/12