Re: [PATCH] hw/riscv: Generate correct "mmu-type" for 32-bit machines

[Alistair Francis]

On Sat, Mar 7, 2020 at 4:49 AM Bin Meng <address@hidden> wrote:
>
> 32-bit machine should have its CPU's "mmu-type" set to "riscv,sv32".
>
> Signed-off-by: Bin Meng <address@hidden>

Reviewed-by: Alistair Francis <address@hidden>

Alistair

> ---
>
>  hw/riscv/sifive_u.c | 4 ++++
>  hw/riscv/spike.c    | 4 ++++
>  hw/riscv/virt.c     | 4 ++++
>  3 files changed, 12 insertions(+)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index d318988..26ea777 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -159,7 +159,11 @@ static void create_fdt(SiFiveUState *s, const struct 
> MemmapEntry *memmap,
>          qemu_fdt_add_subnode(fdt, nodename);
>          /* cpu 0 is the management hart that does not have mmu */
>          if (cpu != 0) {
> +#if defined(TARGET_RISCV32)
> +            qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
> +#else
>              qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
> +#endif
>              isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]);
>          } else {
>              isa = riscv_isa_string(&s->soc.e_cpus.harts[0]);
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index 8823681..6f9a1ba 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -102,7 +102,11 @@ static void create_fdt(SpikeState *s, const struct 
> MemmapEntry *memmap,
>          char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", 
> cpu);
>          char *isa = riscv_isa_string(&s->soc.harts[cpu]);
>          qemu_fdt_add_subnode(fdt, nodename);
> +#if defined(TARGET_RISCV32)
> +        qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
> +#else
>          qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
> +#endif
>          qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
>          qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
>          qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 7f9e1e5..57f532a 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -229,7 +229,11 @@ static void create_fdt(RISCVVirtState *s, const struct 
> MemmapEntry *memmap,
>          char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", 
> cpu);
>          char *isa = riscv_isa_string(&s->soc.harts[cpu]);
>          qemu_fdt_add_subnode(fdt, nodename);
> +#if defined(TARGET_RISCV32)
> +        qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
> +#else
>          qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
> +#endif
>          qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
>          qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
>          qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
> --
> 2.7.4
>
>