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[PULL 31/38] target/riscv: Raise the new execptions when 2nd stage trans
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From: |
Palmer Dabbelt |
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Subject: |
[PULL 31/38] target/riscv: Raise the new execptions when 2nd stage translation fails |
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Date: |
Mon, 2 Mar 2020 16:48:41 -0800 |
From: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu_helper.c | 24 ++++++++++++++++++------
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 584b0c71fb..9e28b19c29 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -587,16 +587,28 @@ static void raise_mmu_exception(CPURISCVState *env,
target_ulong address,
}
switch (access_type) {
case MMU_INST_FETCH:
- cs->exception_index = page_fault_exceptions ?
- RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT;
+ if (riscv_cpu_virt_enabled(env) && !first_stage) {
+ cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
+ } else {
+ cs->exception_index = page_fault_exceptions ?
+ RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT;
+ }
break;
case MMU_DATA_LOAD:
- cs->exception_index = page_fault_exceptions ?
- RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT;
+ if (riscv_cpu_virt_enabled(env) && !first_stage) {
+ cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
+ } else {
+ cs->exception_index = page_fault_exceptions ?
+ RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT;
+ }
break;
case MMU_DATA_STORE:
- cs->exception_index = page_fault_exceptions ?
- RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
+ if (riscv_cpu_virt_enabled(env) && !first_stage) {
+ cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
+ } else {
+ cs->exception_index = page_fault_exceptions ?
+ RISCV_EXCP_STORE_PAGE_FAULT :
RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
+ }
break;
default:
g_assert_not_reached();
--
2.25.0.265.gbab2e86ba0-goog
- Re: [PULL 04/38] target/riscv: Add support for the new execption numbers, (continued)
- [PULL 15/38] target/riscv: Set VS bits in mideleg for Hyp extension, Palmer Dabbelt, 2020/03/02
- [PULL 16/38] target/riscv: Extend the MIE CSR to support virtulisation, Palmer Dabbelt, 2020/03/02
- [PULL 10/38] target/riscv: Dump Hypervisor registers if enabled, Palmer Dabbelt, 2020/03/02
- [PULL 12/38] target/riscv: Add Hypervisor virtual CSRs accesses, Palmer Dabbelt, 2020/03/02
- [PULL 18/38] target/riscv: Add support for virtual interrupt setting, Palmer Dabbelt, 2020/03/02
- [PULL 13/38] target/riscv: Add Hypervisor machine CSRs accesses, Palmer Dabbelt, 2020/03/02
- [PULL 22/38] target/riscv: Add Hypervisor trap return support, Palmer Dabbelt, 2020/03/02
- [PULL 31/38] target/riscv: Raise the new execptions when 2nd stage translation fails,
Palmer Dabbelt <=
- [PULL 30/38] target/riscv: Implement second stage MMU, Palmer Dabbelt, 2020/03/02
- [PULL 19/38] target/ricsv: Flush the TLB on virtulisation mode changes, Palmer Dabbelt, 2020/03/02
- [PULL 23/38] target/riscv: Add hfence instructions, Palmer Dabbelt, 2020/03/02
- [PULL 20/38] target/riscv: Generate illegal instruction on WFI when V=1, Palmer Dabbelt, 2020/03/02
- [PULL 24/38] target/riscv: Remove the hret instruction, Palmer Dabbelt, 2020/03/02
- [PULL 33/38] target/riscv: Add support for the 32-bit MSTATUSH CSR, Palmer Dabbelt, 2020/03/02
- [PULL 29/38] target/riscv: Allow specifying MMU stage, Palmer Dabbelt, 2020/03/02
- [PULL 25/38] target/riscv: Only set TB flags with FP status if enabled, Palmer Dabbelt, 2020/03/02
- [PULL 26/38] target/riscv: Disable guest FP support based on virtual status, Palmer Dabbelt, 2020/03/02
- [PULL 27/38] target/riscv: Mark both sstatus and msstatus_hs as dirty, Palmer Dabbelt, 2020/03/02