Re: [PATCH v5 0/4] target-riscv: support vector extension part 1

[Jim Wilson]

On Wed, Feb 26, 2020 at 2:36 PM Alistair Francis <address@hidden> wrote:
> On Wed, Feb 26, 2020 at 12:09 PM Jim Wilson <address@hidden> wrote:
> > If this rvv 0.7.1 implementation is considered a temporary solution,
> > maybe we can just remove all of this work when the official rvv spec if
> > available?  But presumably it is better if we can have both this
>
> That is generally the plan. When the final spec comes out this will be
> updated and we will only support that.

This solves my problem, but maybe creates one for Alibaba.  They have
apparently fabbed a chip using the 0.7.1 draft of the vector spec
proposal.  So for qemu to properly support their asic, the 0.7.1 draft
support will have to be retained.  But I think SiFive and everyone
else is waiting for the official spec before building asics with
vector support.  If Alibaba will update their processor as the spec
evolves, then maybe this isn't a problem for them.

Jim