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[PATCH v2 14/35] target/riscv: Add virtual register swapping function
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From: |
Alistair Francis |
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Subject: |
[PATCH v2 14/35] target/riscv: Add virtual register swapping function |
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Date: |
Fri, 31 Jan 2020 17:02:12 -0800 |
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu.h | 11 +++++++
target/riscv/cpu_bits.h | 7 +++++
target/riscv/cpu_helper.c | 61 +++++++++++++++++++++++++++++++++++++++
3 files changed, 79 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 42720d65f9..5b889a0065 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -125,6 +125,7 @@ struct CPURISCVState {
target_ulong mstatus;
target_ulong mip;
+
uint32_t miclaim;
target_ulong mie;
@@ -166,6 +167,15 @@ struct CPURISCVState {
target_ulong mtval2;
target_ulong mtinst;
+ /* HS Backup CSRs */
+ target_ulong stvec_hs;
+ target_ulong sscratch_hs;
+ target_ulong sepc_hs;
+ target_ulong scause_hs;
+ target_ulong stval_hs;
+ target_ulong satp_hs;
+ target_ulong mstatus_hs;
+
target_ulong scounteren;
target_ulong mcounteren;
@@ -296,6 +306,7 @@ void riscv_cpu_list(void);
#define cpu_mmu_index riscv_cpu_mmu_index
#ifndef CONFIG_USER_ONLY
+void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index ad6479796c..a24654d137 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -553,4 +553,11 @@
#define SIP_STIP MIP_STIP
#define SIP_SEIP MIP_SEIP
+/* MIE masks */
+#define MIE_SEIE (1 << IRQ_S_EXT)
+#define MIE_UEIE (1 << IRQ_U_EXT)
+#define MIE_STIE (1 << IRQ_S_TIMER)
+#define MIE_UTIE (1 << IRQ_U_TIMER)
+#define MIE_SSIE (1 << IRQ_S_SOFT)
+#define MIE_USIE (1 << IRQ_U_SOFT)
#endif
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 1e28103500..e9d75b45d6 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -82,6 +82,67 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
return false;
}
+void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
+{
+ target_ulong mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
+ MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE;
+ bool current_virt = riscv_cpu_virt_enabled(env);
+
+ g_assert(riscv_has_ext(env, RVH));
+
+#if defined(TARGET_RISCV64)
+ mstatus_mask |= MSTATUS64_UXL;
+#endif
+
+ if (current_virt) {
+ /* Current V=1 and we are about to change to V=0 */
+ env->vsstatus = env->mstatus & mstatus_mask;
+ env->mstatus &= ~mstatus_mask;
+ env->mstatus |= env->mstatus_hs;
+
+ env->vstvec = env->stvec;
+ env->stvec = env->stvec_hs;
+
+ env->vsscratch = env->sscratch;
+ env->sscratch = env->sscratch_hs;
+
+ env->vsepc = env->sepc;
+ env->sepc = env->sepc_hs;
+
+ env->vscause = env->scause;
+ env->scause = env->scause_hs;
+
+ env->vstval = env->sbadaddr;
+ env->sbadaddr = env->stval_hs;
+
+ env->vsatp = env->satp;
+ env->satp = env->satp_hs;
+ } else {
+ /* Current V=0 and we are about to change to V=1 */
+ env->mstatus_hs = env->mstatus & mstatus_mask;
+ env->mstatus &= ~mstatus_mask;
+ env->mstatus |= env->vsstatus;
+
+ env->stvec_hs = env->stvec;
+ env->stvec = env->vstvec;
+
+ env->sscratch_hs = env->sscratch;
+ env->sscratch = env->vsscratch;
+
+ env->sepc_hs = env->sepc;
+ env->sepc = env->vsepc;
+
+ env->scause_hs = env->scause;
+ env->scause = env->vscause;
+
+ env->stval_hs = env->sbadaddr;
+ env->sbadaddr = env->vstval;
+
+ env->satp_hs = env->satp;
+ env->satp = env->vsatp;
+ }
+}
+
bool riscv_cpu_virt_enabled(CPURISCVState *env)
{
if (!riscv_has_ext(env, RVH)) {
--
2.25.0
- [PATCH v2 04/35] target/riscv: Add support for the new execption numbers, (continued)
- [PATCH v2 04/35] target/riscv: Add support for the new execption numbers, Alistair Francis, 2020/01/31
- [PATCH v2 05/35] target/riscv: Rename the H irqs to VS irqs, Alistair Francis, 2020/01/31
- [PATCH v2 06/35] target/riscv: Add the virtulisation mode, Alistair Francis, 2020/01/31
- [PATCH v2 07/35] target/riscv: Add the force HS exception mode, Alistair Francis, 2020/01/31
- [PATCH v2 08/35] target/riscv: Fix CSR perm checking for HS mode, Alistair Francis, 2020/01/31
- [PATCH v2 09/35] target/riscv: Print priv and virt in disas log, Alistair Francis, 2020/01/31
- [PATCH v2 10/35] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2020/01/31
- [PATCH v2 11/35] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2020/01/31
- [PATCH v2 12/35] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2020/01/31
- [PATCH v2 13/35] target/riscv: Add Hypervisor machine CSRs accesses, Alistair Francis, 2020/01/31
- [PATCH v2 14/35] target/riscv: Add virtual register swapping function,
Alistair Francis <=
- [PATCH v2 17/35] target/riscv: Extend the SIP CSR to support virtulisation, Alistair Francis, 2020/01/31
- [PATCH v2 15/35] target/riscv: Set VS bits in mideleg for Hyp extension, Alistair Francis, 2020/01/31
- [PATCH v2 16/35] target/riscv: Extend the MIE CSR to support virtulisation, Alistair Francis, 2020/01/31
- [PATCH v2 18/35] target/riscv: Add support for virtual interrupt setting, Alistair Francis, 2020/01/31
- [PATCH v2 21/35] target/riscv: Add hypvervisor trap support, Alistair Francis, 2020/01/31
- [PATCH v2 19/35] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2020/01/31
- [PATCH v2 20/35] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2020/01/31
- [PATCH v2 25/35] target/riscv: Only set TB flags with FP status if enabled, Alistair Francis, 2020/01/31
- [PATCH v2 22/35] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2020/01/31
- [PATCH v2 24/35] target/riscv: Remove the hret instruction, Alistair Francis, 2020/01/31