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[PATCH v3 1/4] RISC-V: add vector extension field in CPURISCVState
From: |
LIU Zhiwei |
Subject: |
[PATCH v3 1/4] RISC-V: add vector extension field in CPURISCVState |
Date: |
Fri, 3 Jan 2020 11:33:44 +0800 |
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno,offset).
Thus elements can be directly accessed by offset from the first vector
base address.
Signed-off-by: LIU Zhiwei <address@hidden>
---
target/riscv/cpu.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0adb307f32..af66674461 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -93,9 +93,23 @@ typedef struct CPURISCVState CPURISCVState;
#include "pmp.h"
+#define RV_VLEN_MAX 4096
+
struct CPURISCVState {
target_ulong gpr[32];
uint64_t fpr[32]; /* assume both F and D extensions */
+
+ /* vector coprocessor state. */
+ struct {
+ uint64_t vreg[32 * RV_VLEN_MAX / 64];
+ target_ulong vxrm;
+ target_ulong vxsat;
+ target_ulong vl;
+ target_ulong vstart;
+ target_ulong vtype;
+ } vext;
+
+ bool foflag;
target_ulong pc;
target_ulong load_res;
target_ulong load_val;
--
2.23.0