[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v1 17/36] target/riscv: Set VS bits in mideleg for Hyp extension
From: |
Alistair Francis |
Subject: |
[PATCH v1 17/36] target/riscv: Set VS bits in mideleg for Hyp extension |
Date: |
Mon, 9 Dec 2019 10:11:24 -0800 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/csr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a4b598d49a..fc38c45a7e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -449,6 +449,9 @@ static int read_mideleg(CPURISCVState *env, int csrno,
target_ulong *val)
static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val)
{
env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
+ if (riscv_has_ext(env, RVH)) {
+ env->mideleg |= VS_MODE_INTERRUPTS;
+ }
return 0;
}
--
2.24.0
- [PATCH v1 06/36] target/riscv: Rename the H irqs to VS irqs, (continued)
- [PATCH v1 06/36] target/riscv: Rename the H irqs to VS irqs, Alistair Francis, 2019/12/09
- [PATCH v1 07/36] target/riscv: Add the virtulisation mode, Alistair Francis, 2019/12/09
- [PATCH v1 08/36] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/12/09
- [PATCH v1 09/36] target/riscv: Fix CSR perm checking for HS mode, Alistair Francis, 2019/12/09
- [PATCH v1 10/36] target/riscv: Print priv and virt in disas log, Alistair Francis, 2019/12/09
- [PATCH v1 11/36] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/12/09
- [PATCH v1 12/36] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/12/09
- [PATCH v1 13/36] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2019/12/09
- [PATCH v1 14/36] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2019/12/09
- [PATCH v1 16/36] target/riscv: Add virtual register swapping function, Alistair Francis, 2019/12/09
- [PATCH v1 17/36] target/riscv: Set VS bits in mideleg for Hyp extension,
Alistair Francis <=
- [PATCH v1 15/36] target/riscv: Convert mstatus to pointers, Alistair Francis, 2019/12/09
- [PATCH v1 18/36] target/riscv: Extend the MIE CSR to support virtulisation, Alistair Francis, 2019/12/09
- [PATCH v1 19/36] target/riscv: Extend the SIP CSR to support virtulisation, Alistair Francis, 2019/12/09
- [PATCH v1 20/36] target/riscv: Add support for virtual interrupt setting, Alistair Francis, 2019/12/09
- [PATCH v1 21/36] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/12/09
- [PATCH v1 22/36] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/12/09
- [PATCH v1 23/36] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/12/09
- [PATCH v1 24/36] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/12/09
- [PATCH v1 25/36] target/riscv: Add hfence instructions, Alistair Francis, 2019/12/09
- [PATCH v1 26/36] target/riscv: Remove the hret instruction, Alistair Francis, 2019/12/09