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[PATCH v2 16/27] riscv: plic: Always set sip.SEIP bit for HS
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From: |
Alistair Francis |
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Subject: |
[PATCH v2 16/27] riscv: plic: Always set sip.SEIP bit for HS |
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Date: |
Fri, 25 Oct 2019 16:24:03 -0700 |
When the PLIC generates an interrupt ensure we always set it for the SIP
CSR that corresponds to the HS (V=0) register.
Signed-off-by: Alistair Francis <address@hidden>
---
hw/riscv/sifive_plic.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index 98e4304b66..8309e96f64 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -150,7 +150,17 @@ static void sifive_plic_update(SiFivePLICState *plic)
riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP,
BOOL_TO_MASK(level));
break;
case PLICMode_S:
- riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP,
BOOL_TO_MASK(level));
+ if (riscv_cpu_virt_enabled(env)) {
+ if (level) {
+ atomic_or(&env->mip_novirt, MIP_SEIP);
+ g_assert(riscv_cpu_virt_enabled(env));
+ } else {
+ atomic_and(&env->mip_novirt, ~MIP_SEIP);
+ g_assert(riscv_cpu_virt_enabled(env));
+ }
+ } else {
+ riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP,
BOOL_TO_MASK(level));
+ }
break;
default:
break;
--
2.23.0
- [PATCH v2 21/27] target/riscv: Mark both sstatus and vsstatus as dirty, (continued)
- [PATCH v2 21/27] target/riscv: Mark both sstatus and vsstatus as dirty, Alistair Francis, 2019/10/25
- [PATCH v2 13/27] target/riscv: Add support for virtual interrupt setting, Alistair Francis, 2019/10/25
- [PATCH v2 15/27] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/10/25
- [PATCH v2 12/27] target/riscv: Add virtual register swapping function, Alistair Francis, 2019/10/25
- [PATCH v2 14/27] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/10/25
- [PATCH v2 23/27] target/riscv: Allow specifying MMU stage, Alistair Francis, 2019/10/25
- [PATCH v2 24/27] target/riscv: Implement second stage MMU, Alistair Francis, 2019/10/25
- [PATCH v2 25/27] target/riscv: Add support for the 32-bit MSTATUSH CSR, Alistair Francis, 2019/10/25
- [PATCH v2 26/27] target/riscv: Add the MSTATUS_MPV_ISSET helper macro, Alistair Francis, 2019/10/25
- [PATCH v2 27/27] target/riscv: Allow enabling the Hypervisor extension, Alistair Francis, 2019/10/25
- [PATCH v2 16/27] riscv: plic: Always set sip.SEIP bit for HS,
Alistair Francis <=