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[PATCH v2 20/27] target/riscv: Disable guest FP support based on virtual
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From: |
Alistair Francis |
|
Subject: |
[PATCH v2 20/27] target/riscv: Disable guest FP support based on virtual status |
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Date: |
Fri, 25 Oct 2019 16:24:17 -0700 |
When the Hypervisor extension is in use we only enable floating point
support when both status and vsstatus have enabled floating point
support.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu_helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 41cd314f64..79966ac6e6 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -91,6 +91,9 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
bool riscv_cpu_fp_enabled(CPURISCVState *env)
{
if (*env->mstatus & MSTATUS_FS) {
+ if (riscv_cpu_virt_enabled(env) && !(env->vsstatus & MSTATUS_FS)) {
+ return false;
+ }
return true;
}
--
2.23.0
- [PATCH v2 04/27] target/riscv: Add the force HS exception mode, (continued)
- [PATCH v2 04/27] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/10/25
- [PATCH v2 08/27] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/10/25
- [PATCH v2 06/27] target/riscv: Add the Hypervisor CSRs to CPUState, Alistair Francis, 2019/10/25
- [PATCH v2 07/27] target/riscv: Print priv and virt in disas log, Alistair Francis, 2019/10/25
- [PATCH v2 05/27] target/riscv: Fix CSR perm checking for HS mode, Alistair Francis, 2019/10/25
- [PATCH v2 10/27] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2019/10/25
- [PATCH v2 09/27] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/10/25
- [PATCH v2 11/27] target/riscv: Convert mie and mstatus to pointers, Alistair Francis, 2019/10/25
- [PATCH v2 17/27] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/10/25
- [PATCH v2 18/27] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/10/25
- [PATCH v2 20/27] target/riscv: Disable guest FP support based on virtual status,
Alistair Francis <=
- [PATCH v2 19/27] target/riscv: Add hfence instructions, Alistair Francis, 2019/10/25
- [PATCH v2 22/27] target/riscv: Respect MPRV and SPRV for floating point ops, Alistair Francis, 2019/10/25
- [PATCH v2 21/27] target/riscv: Mark both sstatus and vsstatus as dirty, Alistair Francis, 2019/10/25
- [PATCH v2 13/27] target/riscv: Add support for virtual interrupt setting, Alistair Francis, 2019/10/25
- [PATCH v2 15/27] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/10/25
- [PATCH v2 12/27] target/riscv: Add virtual register swapping function, Alistair Francis, 2019/10/25
- [PATCH v2 14/27] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/10/25
- [PATCH v2 23/27] target/riscv: Allow specifying MMU stage, Alistair Francis, 2019/10/25
- [PATCH v2 24/27] target/riscv: Implement second stage MMU, Alistair Francis, 2019/10/25
- [PATCH v2 25/27] target/riscv: Add support for the 32-bit MSTATUSH CSR, Alistair Francis, 2019/10/25