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Re: [PATCH v2 2/7] riscv/sifive_u: Add QSPI memory region
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From: |
Bin Meng |
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Subject: |
Re: [PATCH v2 2/7] riscv/sifive_u: Add QSPI memory region |
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Date: |
Fri, 27 Sep 2019 15:56:54 +0800 |
On Fri, Sep 27, 2019 at 8:51 AM Alistair Francis
<address@hidden> wrote:
>
> The HiFive Unleashed uses is25wp256 SPI NOR flash. There is currently no
> model of this in QEMU, so to allow boot firmware developers to use QEMU
> to target the Unleashed let's add a chunk of memory to represent the QSPI0
> memory mapped flash. This can be targeted using QEMU's -device loader
> command line option.
>
> In the future we can look at adding a model for the is25wp256 flash.
>
> Signed-off-by: Alistair Francis <address@hidden>
> ---
> hw/riscv/sifive_u.c | 8 ++++++++
> include/hw/riscv/sifive_u.h | 1 +
> 2 files changed, 9 insertions(+)
>
Reviewed-by: Bin Meng <address@hidden>
- [PATCH v2 0/7] RISC-V: Add more machine memory, Alistair Francis, 2019/09/26
- [PATCH v2 2/7] riscv/sifive_u: Add QSPI memory region, Alistair Francis, 2019/09/26
- Re: [PATCH v2 2/7] riscv/sifive_u: Add QSPI memory region,
Bin Meng <=
- [PATCH v2 1/7] riscv/sifive_u: Add L2-LIM cache memory, Alistair Francis, 2019/09/26
- [PATCH v2 3/7] riscv/sifive_u: Manually define the machine, Alistair Francis, 2019/09/26
- [PATCH v2 5/7] riscv/virt: Manually define the machine, Alistair Francis, 2019/09/26
- [PATCH v2 4/7] riscv/sifive_u: Add the start-in-flash property, Alistair Francis, 2019/09/26