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[PATCH v1 1/1] target/riscv: Print CPU and privledge in disas
From: |
Alistair Francis |
Subject: |
[PATCH v1 1/1] target/riscv: Print CPU and privledge in disas |
Date: |
Thu, 26 Sep 2019 17:45:30 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/translate.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index adeddb85f6..537af0003e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -810,7 +810,14 @@ static void riscv_tr_tb_stop(DisasContextBase *dcbase,
CPUState *cpu)
static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
{
+#ifndef CONFIG_USER_ONLY
+ RISCVCPU *rvcpu = RISCV_CPU(cpu);
+ CPURISCVState *env = &rvcpu->env;
+#endif
qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
+#ifndef CONFIG_USER_ONLY
+ qemu_log("CPU: %d; priv: "TARGET_FMT_ld"\n", cpu->cpu_index, env->priv);
+#endif
log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
}
--
2.23.0
- [PATCH v1 1/1] target/riscv: Print CPU and privledge in disas,
Alistair Francis <=