Re: [PATCH V3] target/riscv: Bugfix reserved bits in PTE for RV64

[Guo Ren]

On Wed, Sep 25, 2019 at 1:35 PM Bin Meng <address@hidden> wrote:
>
> On Wed, Sep 25, 2019 at 12:49 PM <address@hidden> wrote:
> >
> > From: Guo Ren <address@hidden>
> >
>
> nits: the title is probably better to be rephrased to: Ignore reserved
> bits when calculating PPN for RV64
Yes, I forgot change the title.

>
> > Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we
> > need to ignore them. They can not be a part of ppn.
>
> nits: cannot
Thx

>
> >
> > 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
> >    4.4 Sv39: Page-Based 39-bit Virtual-Memory System
> >    4.5 Sv48: Page-Based 48-bit Virtual-Memory System
> >
> > Signed-off-by: Guo Ren <address@hidden>
> > Reviewed-by: Liu Zhiwei <address@hidden>
> > ---
> >  target/riscv/cpu_bits.h   | 3 +++
> >  target/riscv/cpu_helper.c | 4 +++-
> >  2 files changed, 6 insertions(+), 1 deletion(-)
> > ---
> > Changelog V3:
>
> nits: normally we put changelog before the changed file summary above,
> and there is no need to put another ---
OK, just remove ---

>
> >  - Use UUL define for PTE_RESERVED.
> >  - Keep ppn >> PTE_PPN_SHIFT
> >
> > Changelog V2:
> >  - Bugfix pte destroyed cause boot fail
> >  - Change to AND with a mask instead of shifting both directions
> >
> > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> > index e998348..cdc62a8 100644
> > --- a/target/riscv/cpu_bits.h
> > +++ b/target/riscv/cpu_bits.h
> > @@ -470,6 +470,9 @@
> >  #define PTE_D               0x080 /* Dirty */
> >  #define PTE_SOFT            0x300 /* Reserved for Software */
> >
> > +/* Reserved highest 10 bits in PTE */
> > +#define PTE_RESERVED        0xFFC0000000000000ULL
>
> Can we define the macro for RV32 too, so that (see below)
OK

>
> > +
> >  /* Page table PPN shift amount */
> >  #define PTE_PPN_SHIFT       10
> >
> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> > index 87dd6a6..7e04ff5 100644
> > --- a/target/riscv/cpu_helper.c
> > +++ b/target/riscv/cpu_helper.c
> > @@ -258,10 +258,12 @@ restart:
> >          }
> >  #if defined(TARGET_RISCV32)
> >          target_ulong pte = ldl_phys(cs->as, pte_addr);
> > +        hwaddr ppn = pte;
> >  #elif defined(TARGET_RISCV64)
> >          target_ulong pte = ldq_phys(cs->as, pte_addr);
> > +        hwaddr ppn = pte & ~PTE_RESERVED;
> >  #endif
> > -        hwaddr ppn = pte >> PTE_PPN_SHIFT;
> > +        ppn = ppn >> PTE_PPN_SHIFT;
>
> we can just do this in this single line?
Yes

-- 
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/