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[Qemu-riscv] [PULL 08/48] target/riscv: Update the Hypervisor CSRs to v0
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 08/48] target/riscv: Update the Hypervisor CSRs to v0.4 |
Date: |
Wed, 18 Sep 2019 07:56:00 -0700 |
From: Alistair Francis <address@hidden>
Update the Hypervisor CSR addresses to match the v0.4 spec.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu_bits.h | 35 ++++++++++++++++++-----------------
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 11f971ad5d..e99834856c 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -173,6 +173,24 @@
#define CSR_SPTBR 0x180
#define CSR_SATP 0x180
+/* Hpervisor CSRs */
+#define CSR_HSTATUS 0x600
+#define CSR_HEDELEG 0x602
+#define CSR_HIDELEG 0x603
+#define CSR_HCOUNTERNEN 0x606
+#define CSR_HGATP 0x680
+
+#if defined(TARGET_RISCV32)
+#define HGATP_MODE SATP32_MODE
+#define HGATP_VMID SATP32_ASID
+#define HGATP_PPN SATP32_PPN
+#endif
+#if defined(TARGET_RISCV64)
+#define HGATP_MODE SATP64_MODE
+#define HGATP_VMID SATP64_ASID
+#define HGATP_PPN SATP64_PPN
+#endif
+
/* Physical Memory Protection */
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPCFG1 0x3a1
@@ -206,23 +224,6 @@
#define CSR_DPC 0x7b1
#define CSR_DSCRATCH 0x7b2
-/* Hpervisor CSRs */
-#define CSR_HSTATUS 0xa00
-#define CSR_HEDELEG 0xa02
-#define CSR_HIDELEG 0xa03
-#define CSR_HGATP 0xa80
-
-#if defined(TARGET_RISCV32)
-#define HGATP_MODE SATP32_MODE
-#define HGATP_ASID SATP32_ASID
-#define HGATP_PPN SATP32_PPN
-#endif
-#if defined(TARGET_RISCV64)
-#define HGATP_MODE SATP64_MODE
-#define HGATP_ASID SATP64_ASID
-#define HGATP_PPN SATP64_PPN
-#endif
-
/* Performance Counters */
#define CSR_MHPMCOUNTER3 0xb03
#define CSR_MHPMCOUNTER4 0xb04
--
2.21.0
- [Qemu-riscv] [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 01/48] riscv: sifive_u: Add support for loading initrd, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 02/48] riscv: sivive_u: Add dummy serial clock and aliases entry for uart, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 03/48] riscv: sifive_u: Fix clock-names property for ethernet node, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 04/48] target/riscv/pmp: Restrict priviledged PMP to system-mode emulation, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 05/48] target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 06/48] riscv: plic: Remove unused interrupt functions, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 07/48] target/riscv: Create function to test if FP is enabled, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 08/48] target/riscv: Update the Hypervisor CSRs to v0.4,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 09/48] riscv: rv32: Root page table address can be larger than 32-bit, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 11/48] riscv: Resolve full path of the given bios image, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 13/48] riscv: sifive_test: Add reset functionality, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 12/48] riscv: hmp: Add a command to show virtual memory mappings, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 14/48] riscv: hw: Remove duplicated "hw/hw.h" inclusion, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 15/48] riscv: hw: Remove superfluous "linux, phandle" property, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 16/48] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 17/48] riscv: hw: Remove not needed PLIC properties in device tree, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 18/48] riscv: hw: Change create_fdt() to return void, Palmer Dabbelt, 2019/09/18