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[Qemu-riscv] [PULL 06/48] riscv: plic: Remove unused interrupt functions
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From: |
Palmer Dabbelt |
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Subject: |
[Qemu-riscv] [PULL 06/48] riscv: plic: Remove unused interrupt functions |
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Date: |
Wed, 18 Sep 2019 07:55:58 -0700 |
From: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Jonathan Behrens <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Chih-Min Chao <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/sifive_plic.c | 12 ------------
include/hw/riscv/sifive_plic.h | 3 ---
2 files changed, 15 deletions(-)
diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index 64a1a10380..98e4304b66 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -162,18 +162,6 @@ static void sifive_plic_update(SiFivePLICState *plic)
}
}
-void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq)
-{
- sifive_plic_set_pending(plic, irq, true);
- sifive_plic_update(plic);
-}
-
-void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq)
-{
- sifive_plic_set_pending(plic, irq, false);
- sifive_plic_update(plic);
-}
-
static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid)
{
int i, j;
diff --git a/include/hw/riscv/sifive_plic.h b/include/hw/riscv/sifive_plic.h
index b0edba2884..4421e81249 100644
--- a/include/hw/riscv/sifive_plic.h
+++ b/include/hw/riscv/sifive_plic.h
@@ -69,9 +69,6 @@ typedef struct SiFivePLICState {
uint32_t aperture_size;
} SiFivePLICState;
-void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq);
-void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq);
-
DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
uint32_t num_sources, uint32_t num_priorities,
uint32_t priority_base, uint32_t pending_base,
--
2.21.0
- [Qemu-riscv] [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 01/48] riscv: sifive_u: Add support for loading initrd, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 02/48] riscv: sivive_u: Add dummy serial clock and aliases entry for uart, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 03/48] riscv: sifive_u: Fix clock-names property for ethernet node, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 04/48] target/riscv/pmp: Restrict priviledged PMP to system-mode emulation, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 05/48] target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 06/48] riscv: plic: Remove unused interrupt functions,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 07/48] target/riscv: Create function to test if FP is enabled, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 08/48] target/riscv: Update the Hypervisor CSRs to v0.4, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 09/48] riscv: rv32: Root page table address can be larger than 32-bit, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 11/48] riscv: Resolve full path of the given bios image, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 13/48] riscv: sifive_test: Add reset functionality, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 12/48] riscv: hmp: Add a command to show virtual memory mappings, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 14/48] riscv: hw: Remove duplicated "hw/hw.h" inclusion, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 15/48] riscv: hw: Remove superfluous "linux, phandle" property, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 16/48] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Palmer Dabbelt, 2019/09/18