[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 06/17] RISC-V: add vector extens
From: |
Richard Henderson |
Subject: |
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 06/17] RISC-V: add vector extension fault-only-first implementation |
Date: |
Thu, 12 Sep 2019 10:32:20 -0400 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 |
On 9/11/19 2:25 AM, liuzhiwei wrote:
> diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
> index 12aa3c0..d673fa5 100644
> --- a/linux-user/riscv/cpu_loop.c
> +++ b/linux-user/riscv/cpu_loop.c
> @@ -41,6 +41,13 @@ void cpu_loop(CPURISCVState *env)
> sigcode = 0;
> sigaddr = 0;
>
> + if (env->foflag) {
> + if (env->vfp.vl != 0) {
> + env->foflag = false;
> + env->pc += 4;
> + continue;
> + }
> + }
> switch (trapnr) {
> case EXCP_INTERRUPT:
> /* just indicate that signals should be handled asap */
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index e32b612..405caf6 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -521,6 +521,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> [PRV_H] = RISCV_EXCP_H_ECALL,
> [PRV_M] = RISCV_EXCP_M_ECALL
> };
> + if (env->foflag) {
> + if (env->vfp.vl != 0) {
> + env->foflag = false;
> + env->pc += 4;
> + return;
> + }
> + }
I renew my objection to this FOFLAG mechanism. I believe, but have no proof,
that this will race between different types of interrupts. Once again I
present the ARM SVE first-fault helpers as proof that there is another way.
Otherwise, all of the same comments from the normal loads apply.
r~
- [Qemu-riscv] [PATCH v2 03/17] RISC-V: support vector extension csr, (continued)
- [Qemu-riscv] [PATCH v2 03/17] RISC-V: support vector extension csr, liuzhiwei, 2019/09/11
- [Qemu-riscv] [PATCH v2 02/17] RISC-V: turn on vector extension from command line by cfg.ext_v Property, liuzhiwei, 2019/09/11
- [Qemu-riscv] [PATCH v2 04/17] RISC-V: add vector extension configure instruction, liuzhiwei, 2019/09/11
- [Qemu-riscv] [PATCH v2 06/17] RISC-V: add vector extension fault-only-first implementation, liuzhiwei, 2019/09/11
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 06/17] RISC-V: add vector extension fault-only-first implementation,
Richard Henderson <=
- [Qemu-riscv] [PATCH v2 07/17] RISC-V: add vector extension atomic instructions, liuzhiwei, 2019/09/11
- [Qemu-riscv] [PATCH v2 09/17] RISC-V: add vector extension integer instructions part2, bit/shift, liuzhiwei, 2019/09/11
- [Qemu-riscv] [PATCH v2 10/17] RISC-V: add vector extension integer instructions part3, cmp/min/max, liuzhiwei, 2019/09/11
- [Qemu-riscv] [PATCH v2 05/17] RISC-V: add vector extension load and store instructions, liuzhiwei, 2019/09/11
- [Qemu-riscv] [PATCH v2 08/17] RISC-V: add vector extension integer instructions part1, add/sub/adc/sbc, liuzhiwei, 2019/09/11