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[Qemu-riscv] [PULL 25/47] riscv: sifive_e: prci: Update the PRCI registe
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 25/47] riscv: sifive_e: prci: Update the PRCI register block size |
Date: |
Tue, 10 Sep 2019 12:04:51 -0700 |
From: Bin Meng <address@hidden>
Currently the PRCI register block size is set to 0x8000, but in fact
0x1000 is enough, which is also what the manual says.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Chih-Min Chao <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/sifive_e_prci.c | 2 +-
include/hw/riscv/sifive_e_prci.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_e_prci.c b/hw/riscv/sifive_e_prci.c
index bfe9b13a67..a1c0d44f18 100644
--- a/hw/riscv/sifive_e_prci.c
+++ b/hw/riscv/sifive_e_prci.c
@@ -87,7 +87,7 @@ static void sifive_e_prci_init(Object *obj)
SiFiveEPRCIState *s = SIFIVE_E_PRCI(obj);
memory_region_init_io(&s->mmio, obj, &sifive_e_prci_ops, s,
- TYPE_SIFIVE_E_PRCI, 0x8000);
+ TYPE_SIFIVE_E_PRCI, SIFIVE_E_PRCI_REG_SIZE);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
s->hfrosccfg = (SIFIVE_E_PRCI_HFROSCCFG_RDY | SIFIVE_E_PRCI_HFROSCCFG_EN);
diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/riscv/sifive_e_prci.h
index c4b76aa17a..698b0b451c 100644
--- a/include/hw/riscv/sifive_e_prci.h
+++ b/include/hw/riscv/sifive_e_prci.h
@@ -47,6 +47,8 @@ enum {
SIFIVE_E_PRCI_PLLOUTDIV_DIV1 = (1 << 8)
};
+#define SIFIVE_E_PRCI_REG_SIZE 0x1000
+
#define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci"
#define SIFIVE_E_PRCI(obj) \
--
2.21.0
- [Qemu-riscv] [PULL 15/47] riscv: hw: Remove superfluous "linux, phandle" property, (continued)
- [Qemu-riscv] [PULL 15/47] riscv: hw: Remove superfluous "linux, phandle" property, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 16/47] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 17/47] riscv: hw: Remove not needed PLIC properties in device tree, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 18/47] riscv: hw: Change create_fdt() to return void, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 19/47] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 20/47] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 22/47] riscv: sifive_u: Remove the unnecessary include of prci header, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 21/47] riscv: roms: Remove executable attribute of opensbi images, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 24/47] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 23/47] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 25/47] riscv: sifive_e: prci: Update the PRCI register block size,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 27/47] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 26/47] riscv: sifive_e: Drop sifive_mmio_emulate(), Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 29/47] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 28/47] riscv: hart: Extract hart realize to a separate routine, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 30/47] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 31/47] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 32/47] riscv: sifive_u: Update PLIC hart topology configuration string, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 33/47] riscv: sifive: Implement PRCI model for FU540, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 35/47] riscv: sifive_u: Add PRCI block to the SoC, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 36/47] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes, Palmer Dabbelt, 2019/09/11