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[Qemu-riscv] [PATCH v8 32/32] riscv: sifive_u: Update model and compatib
From: |
Bin Meng |
Subject: |
[Qemu-riscv] [PATCH v8 32/32] riscv: sifive_u: Update model and compatible strings in device tree |
Date: |
Fri, 6 Sep 2019 09:20:19 -0700 |
This updates model and compatible strings to use the same strings
as used in the Linux kernel device tree (hifive-unleashed-a00.dts).
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_u.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 507a6e2..ca9f7fe 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -96,8 +96,9 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
exit(1);
}
- qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
- qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
+ qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
+ qemu_fdt_setprop_string(fdt, "/", "compatible",
+ "sifive,hifive-unleashed-a00");
qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
--
2.7.4
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, (continued)
- [Qemu-riscv] [PATCH v8 20/32] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 23/32] riscv: sifive_u: Add PRCI block to the SoC, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 26/32] riscv: sifive_u: Change UART node name in device tree, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 24/32] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 25/32] riscv: sifive_u: Update UART base addresses and IRQs, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 21/32] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 19/32] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 29/32] riscv: sifive_u: Instantiate OTP memory with a serial number, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 32/32] riscv: sifive_u: Update model and compatible strings in device tree,
Bin Meng <=
- [Qemu-riscv] [PATCH v8 31/32] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 28/32] riscv: sifive: Implement a model for SiFive FU540 OTP, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 30/32] riscv: sifive_u: Fix broken GEM support, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 27/32] riscv: roms: Update default bios for sifive_u machine, Bin Meng, 2019/09/06