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[Qemu-riscv] [PATCH v7 24/30] riscv: sifive_u: Change UART node name in
From: |
Bin Meng |
Subject: |
[Qemu-riscv] [PATCH v7 24/30] riscv: sifive_u: Change UART node name in device tree |
Date: |
Sat, 31 Aug 2019 19:53:05 -0700 |
OpenSBI for fu540 does DT fix up (see fu540_modify_dt()) by updating
chosen "stdout-path" to point to "/soc/serial@...", and U-Boot will
use this information to locate the serial node and probe its driver.
However currently we generate the UART node name as "/soc/uart@...",
causing U-Boot fail to find the serial node in DT.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_u.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index c7b9f96..d970037 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -286,7 +286,7 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
uartclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
g_free(nodename);
- nodename = g_strdup_printf("/soc/uart@%lx",
+ nodename = g_strdup_printf("/soc/serial@%lx",
(long)memmap[SIFIVE_U_UART0].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
--
2.7.4
- [Qemu-riscv] [PATCH v7 22/30] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes, (continued)
- [Qemu-riscv] [PATCH v7 22/30] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 23/30] riscv: sifive_u: Update UART base addresses and IRQs, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 18/30] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 12/30] riscv: sifive_e: Drop sifive_mmio_emulate(), Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 16/30] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 19/30] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 24/30] riscv: sifive_u: Change UART node name in device tree,
Bin Meng <=
- [Qemu-riscv] [PATCH v7 21/30] riscv: sifive_u: Add PRCI block to the SoC, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 17/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 27/30] riscv: sifive_u: Instantiate OTP memory with a serial number, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 30/30] riscv: sifive_u: Update model and compatible strings in device tree, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 26/30] riscv: sifive: Implement a model for SiFive FU540 OTP, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 28/30] riscv: sifive_u: Fix broken GEM support, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 25/30] riscv: roms: Update default bios for sifive_u machine, Bin Meng, 2019/08/31