Re: [Qemu-riscv] [PATCH v2] RISC-V: Select FPU gdb xml file based on the supported extensions

[Georg Kotheimer]

On Tuesday, 20 August 2019 22:06:51 CEST Jim Wilson wrote:
> The current XML files were identical to the XML files in gdb when
> implemented.  This seems to be existing practice, as this is true of all
> of the other targets I looked at when I implemented this.  Also, the
> file names are the same with a / replaced with a -.  These files are in
> the gdb/features/riscv dir in a gdb source tree.  It would be a shame to
> break this.  I'm not sure if they are still identical.  The gdb copies
> might have been updated since then, and may need to be copied into qemu
> to update qemu, but we don't have a dedicated gdb/qemu maintainer to do
> this.
> 
> I don't see a need to remove the fp csr's from the csr list.  There are
> other extension dependent CSRs, like hypervisor ones. I think it makes
> more sense for the csr list to contain all of the csrs, and then disable
> access to them if that extension is not enabled.  If there is a good
> reason to require changes to the csr XML files, then it probably should
> be discussed with the gdb developers too, so that the gdb and qemu
> copies of the files remain consistent.
> 
> Fixing the rvf/rvd 32/64-bit support is good.  That is a bug in my
> original implementation.
> 
> Jim

My motivation behind renaming the xml files was to work against the 
misconception that e.g. 64bit-cpu and 64bit-fpu are related to one another. 
But of course, 32bit-fpu and 64bit-fpu is technically not incorrect.

Regarding the removal of the fp csrs from the csr list: I found it confusing 
that the fp csr registers were listed in two files. In addition the bitsize of 
the fp csr registers was stated as 64 in riscv-64bit-csr.xml, wheras the other 
xml files (32bit-csr, 32bit-fpu and 64bit-fpu) stated 32, in accordance with 
the RISC-V ISA specification.
Then I had a look at the gdb source code, and came to the conclusion that gdb 
does not use the fp csr registers from the org.gnu.gdb.riscv.csr feaure set, 
but instead the ones from org.gnu.gdb.riscv.fpu. Therefore, I decided to 
remove the fp csr registers from the csr list.
However, as I don't have any prior experience with QEMU or gdb development is 
quite likely that I misinterpreted or overlooked something.

For now I prepared a third version of the patch that only fixes the rvf/rvd 
32/64-bit support.

Georg