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Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 05/28] riscv: hart: Support hete

From: Richard Henderson
Subject: Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 05/28] riscv: hart: Support heterogeneous harts population
Date: Sun, 11 Aug 2019 08:56:56 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0

On 8/11/19 1:06 AM, Bin Meng wrote:
> +        /* heterogeneous harts */
> +        while (tmp_type) {
> +            if (n >= s->num_harts) {
> +                break;
> +            }
> +            riscv_hart_realize(s, n++, tmp_type, errp);
> +            last_type = tmp_type;
> +            tmp_type = strtok(NULL, ",");
> +        }

You need to create clusters for each cpu type.

In particular, E51 does not have the fpu that U54 does, and so we need to
generate different code for each cluster.

Because each cluster generates different TBs, you'll minimize code generation
if you do more than just create one per cpu, e.g. pop these cpu type names into
a GHashTable as you create each cluster.

The only other example of clusters in tree is hw/arm/armsse.c.  Note that board
has one cpu per cluster, as each cpu may be configured differently via other
property settings.


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