On Thu, Aug 8, 2019 at 7:29
PM Aleksandar Markovic <address@hidden
On Thu, Aug 8, 2019 at
11:52 AM liuzhiwei <address@hidden>
> Hi all,
> My workmate and I have been working on Vector
& Dsp extension, and
> I'd like to share develop status with folks.
> The spec references for Vector extension is
> riscv-p-spec-0.5 for DSP extension.
I will not answer your questions directly, however I want to
bring to you
and others another perspective on this situation.
First, please provide the link to the specifications. Via
Google, I found
that "riscv-v-spec-0.7.1" is titled "Working draft of the
proposed RISC-V V
vector extension". I could not find "riscv-p-spec-0.5".
I am not sure what the QEMU policy towards "working draft
proposal" type of
specification is. Peter, can you perhaps clarify that or any
As for riscv-v-spec 0.7.1, it is first stable spec for
target software development
though the name is working draft. The architecture
skeleton is fix and most of
work are focusing the issues related to
micro-architecture implementation complexity.
Sifive has released an open source implementation on
spike simulation and Imperas also
provides another implementation with its binary
simulator. I think it is worth to include the extension
in Qemu at this moment.
As for riscv-p-spec-0.5, I think Andes has fully
supported this extension and should release more
detailed spec in the near future (described Riscv
Technical Update 2019/06).
They have implement lots of DSP kernel based on this
extension and also provided impressed
performance result. It is also worth to be reviewed (at
least [RFC]) if the detailed spec is public.