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Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: rv32: Root page table addre

From: Palmer Dabbelt
Subject: Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: rv32: Root page table address can be larger than 32-bit
Date: Wed, 7 Aug 2019 13:55:23 -0700

On Thu, Aug 1, 2019 at 7:58 AM Bin Meng <address@hidden> wrote:
On Thu, Aug 1, 2019 at 10:16 PM Richard Henderson
<address@hidden> wrote:
> On 7/31/19 6:53 PM, Bin Meng wrote:
> > I am not sure how (idx * ptesize) could overflow. It represents the
> > offset by a page table which is [0, 4096).
> You're right, I mis-read what was going on there.
> However, lower down, "target_ulong ppn" needs to be promoted to hwaddr, so that
>     ppn = pte >> PTE_PPN_SHIFT;
>     ...
>     base = ppn << PGSHIFT;
> does not overflow.  (Which is the part of the page table walk that I thought I
> had gleaned from the patch without actually reading the entire function.)

Ah, yes. ppn should be promoted. Thanks for the review!

Did I miss a v2? 

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