[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-riscv] [PATCH v2 05/28] riscv: hart: Support heterogeneous harts p
From: |
Bin Meng |
Subject: |
[Qemu-riscv] [PATCH v2 05/28] riscv: hart: Support heterogeneous harts population |
Date: |
Wed, 7 Aug 2019 00:45:01 -0700 |
At present we only allow symmetric harts to be created. In order to
support heterogeneous harts like SiFive FU540, update hart array's
"cpu-type" property to allow cpu type to be set per hart, separated
by delimiter ",". The frist cpu type before the delimiter is assigned
to hart 0, and the second cpu type before delimiter is assigned to
hart 1, and so on.
If the total number of cpu types supplied in "cpu-type" property is
less than number of maximum harts, the last cpu type in the property
will be used to populate remaining harts.
Signed-off-by: Bin Meng <address@hidden>
---
Changes in v2: None
hw/riscv/riscv_hart.c | 48 +++++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 45 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index 3dd1c6a..27093e0 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -58,13 +58,55 @@ static void riscv_hart_realize(RISCVHartArrayState *s, int
hart,
static void riscv_harts_realize(DeviceState *dev, Error **errp)
{
RISCVHartArrayState *s = RISCV_HART_ARRAY(dev);
- int n;
+ char *cpu_types;
+ char *first_type, *last_type, *tmp_type;
+ int n = 0;
s->harts = g_new0(RISCVCPU, s->num_harts);
- for (n = 0; n < s->num_harts; n++) {
- riscv_hart_realize(s, n, s->cpu_type, errp);
+ /* we should not touch the original s->cpu_type */
+ cpu_types = g_strdup(s->cpu_type);
+
+ /*
+ * Expect s->cpu_type property was initialized this way:
+ *
+ * "cpu-type-a": symmetric harts
+ * "cpu-type-a,cpu-type-b,cpu-type-c": heterogeneous harts
+ *
+ * For heterogeneous harts, hart cpu types are separated by delimiter ",".
+ * The frist cpu type before the delimiter is assigned to hart 0, and the
+ * second cpu type before delimiter is assigned to hart 1, and so on.
+ *
+ * If the total number of cpu types is less than s->num_harts, the last
+ * cpu type in s->cpu_type will be used to populate remaining harts.
+ */
+
+ first_type = strtok(cpu_types, ",");
+ riscv_hart_realize(s, n++, first_type, errp);
+ tmp_type = strtok(NULL, ",");
+ if (!tmp_type) {
+ /* symmetric harts */
+ for (; n < s->num_harts; n++) {
+ riscv_hart_realize(s, n, first_type, errp);
+ }
+ } else {
+ /* heterogeneous harts */
+ while (tmp_type) {
+ if (n >= s->num_harts) {
+ break;
+ }
+ riscv_hart_realize(s, n++, tmp_type, errp);
+ last_type = tmp_type;
+ tmp_type = strtok(NULL, ",");
+ }
+
+ /* populate remaining harts using the last cpu type in s->cpu_type */
+ for (; n < s->num_harts; n++) {
+ riscv_hart_realize(s, n, last_type, errp);
+ }
}
+
+ g_free(cpu_types);
}
static void riscv_harts_class_init(ObjectClass *klass, void *data)
--
2.7.4
- [Qemu-riscv] [PATCH v2 08/28] riscv: sifive_u: Update PLIC hart topology configuration string, (continued)
- [Qemu-riscv] [PATCH v2 08/28] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/07
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Alistair Francis, 2019/08/09
- [Qemu-riscv] [PATCH v2 10/28] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 19/28] riscv: sifive_u: Instantiate OTP memory with a serial number, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 05/28] riscv: hart: Support heterogeneous harts population,
Bin Meng <=
- [Qemu-riscv] [PATCH v2 13/28] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 22/28] riscv: sifive_u: Generate an aliases node in the device tree, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 17/28] riscv: sifive_u: Change UART node name in device tree, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 16/28] riscv: sifive_u: Add PRCI block to the SoC, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 14/28] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 25/28] riscv: hw: Remove not needed PLIC properties in device tree, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 18/28] riscv: hw: Implement a model for SiFive FU540 OTP, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 24/28] riscv: sifive_u: Support loading initramfs, Bin Meng, 2019/08/07