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Re: [Qemu-riscv] [PULL 04/32] target/riscv: Implement riscv_cpu_unassign
Re: [Qemu-riscv] [PULL 04/32] target/riscv: Implement riscv_cpu_unassigned_access
Thu, 1 Aug 2019 16:39:17 +0100
On Wed, 3 Jul 2019 at 09:41, Palmer Dabbelt <address@hidden> wrote:
> From: Michael Clark <address@hidden>
> This patch adds support for the riscv_cpu_unassigned_access call
> and will raise a load or store access fault.
> Signed-off-by: Michael Clark <address@hidden>
> [Changes by AF:
> - Squash two patches and rewrite commit message
> - Set baddr to the access address
> Signed-off-by: Alistair Francis <address@hidden>
> Reviewed-by: Palmer Dabbelt <address@hidden>
> Signed-off-by: Palmer Dabbelt <address@hidden>
Oops, I missed seeing this go by. The do_unassigned_access
hook is deprecated and you should drop this and use
the do_transaction_failed hook instead.
The distinction between the two is that do_unassigned_access
will end up being called for any failing access, including
not just "normal" guest accesses but also for bad accesses
that happen during page table walks (which often want to
be reported to the guest differently) and also accesses
by random devices like DMA controllers (where throwing a
cpu exception is always a bug).
Changing the hook implementation itself should be straightforward;
commit 6ad4d7eed05a1e23537f is an example of doing that on Alpha.
You also want to check all the places in your target code that
do physical memory accesses, determine what the right behaviour
if they get a bus fault is, and implement that (or at least put
in TODO comments).
- Re: [Qemu-riscv] [PULL 04/32] target/riscv: Implement riscv_cpu_unassigned_access,
Peter Maydell <=