Re: [Qemu-riscv] [Qemu-devel] [PATCH v2] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren

[Alistair Francis]

On Mon, Jul 1, 2019 at 8:56 AM <address@hidden> wrote:
>
> From: Jonathan Behrens <address@hidden>
>
> QEMU currently always triggers an illegal instruction exception when
> code attempts to read the time CSR. This is valid behavor, but only if
> the TM bit in mcounteren is hardwired to zero. This change also
> corrects mcounteren and scounteren CSRs to be 32-bits on both 32-bit
> and 64-bit targets.
>
> Signed-off-by: Jonathan Behrens <address@hidden>

Reviewed-by: Alistair Francis <address@hidden>

Alistair

> ---
>  target/riscv/cpu.h      | 4 ++--
>  target/riscv/cpu_bits.h | 5 +++++
>  target/riscv/csr.c      | 2 +-
>  3 files changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 0adb307f32..2d0cbe9c78 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -151,8 +151,8 @@ struct CPURISCVState {
>      target_ulong mcause;
>      target_ulong mtval;  /* since: priv-1.10.0 */
>
> -    target_ulong scounteren;
> -    target_ulong mcounteren;
> +    uint32_t scounteren;
> +    uint32_t mcounteren;
>
>      target_ulong sscratch;
>      target_ulong mscratch;
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 11f971ad5d..0ea1e1caf5 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -532,4 +532,9 @@
>  #define SIP_STIP                           MIP_STIP
>  #define SIP_SEIP                           MIP_SEIP
>
> +/* mcounteren CSR bits */
> +#define MCOUNTEREN_CY                      0x1
> +#define MCOUNTEREN_TM                      0x2
> +#define MCOUNTEREN_IR                      0x4
> +
>  #endif
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index e0d4586760..8425a6d2bd 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -473,7 +473,7 @@ static int write_mcounteren(CPURISCVState *env, int 
> csrno, target_ulong val)
>      if (env->priv_ver < PRIV_VERSION_1_10_0) {
>          return -1;
>      }
> -    env->mcounteren = val;
> +    env->mcounteren = val & ~MCOUNTEREN_TM;
>      return 0;
>  }
>
> --
> 2.22.0
>