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Re: [Qemu-riscv] [Qemu-devel] [PATCHv4 3/6] RISC-V: Check for the effect
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-riscv] [Qemu-devel] [PATCHv4 3/6] RISC-V: Check for the effective memory privilege mode during PMP checks |
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Date: |
Thu, 27 Jun 2019 19:00:53 +0200 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 |
On 6/27/19 2:18 PM, Hesham Almatary wrote:
> @@ -392,19 +392,27 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address,
> int size,
> int prot;
> bool pmp_violation = false;
> int ret = TRANSLATE_FAIL;
> + int mode = mmu_idx;
>
> qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
> __func__, address, access_type, mmu_idx);
>
> ret = get_physical_address(env, &pa, &prot, address, access_type,
> mmu_idx);
>
> + if (mode == PRV_M && access_type != MMU_INST_FETCH) {
> + if (get_field(env->mstatus, MSTATUS_MPRV)) {
> + mode = get_field(env->mstatus, MSTATUS_MPP);
> + }
> + }
This hunk looks like it belongs in riscv_cpu_mmu_index instead.
Passing the (corrected) mmu_idx on to pmp_hart_has_privs looks right.
r~
- [Qemu-riscv] [PATCHv4 1/6] RISC-V: Only Check PMP if MMU translation succeeds, Hesham Almatary, 2019/06/27
- [Qemu-riscv] [PATCHv4 2/6] RISC-V: Raise access fault exceptions on PMP violations, Hesham Almatary, 2019/06/27
- [Qemu-riscv] [PATCHv4 3/6] RISC-V: Check for the effective memory privilege mode during PMP checks, Hesham Almatary, 2019/06/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCHv4 3/6] RISC-V: Check for the effective memory privilege mode during PMP checks,
Richard Henderson <=
- [Qemu-riscv] [PATCHv4 6/6] RISC-V: Fix a PMP check with the correct access size, Hesham Almatary, 2019/06/27
- [Qemu-riscv] [PATCHv4 4/6] RISC-V: Check PMP during Page Table Walks, Hesham Almatary, 2019/06/27
- [Qemu-riscv] [PATCHv4 5/6] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off, Hesham Almatary, 2019/06/27