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Re: [Qemu-riscv] [PULL 01/29] SiFive RISC-V GPIO Device

From: Palmer Dabbelt
Subject: Re: [Qemu-riscv] [PULL 01/29] SiFive RISC-V GPIO Device
Date: Fri, 14 Jun 2019 05:10:12 -0700 (PDT)

On Thu, 30 May 2019 03:57:12 PDT (-0700), Peter Maydell wrote:
On Sun, 26 May 2019 at 02:10, Palmer Dabbelt <address@hidden> wrote:

From: Fabien Chouteau <address@hidden>

QEMU model of the GPIO device on the SiFive E300 series SOCs.

The pins are not used by a board definition yet, however this
implementation can already be used to trigger GPIO interrupts from the
software by configuring a pin as both output and input.

Signed-off-by: Fabien Chouteau <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>

Hi; this patch causes Coverity to complain about a memory
leak (CID 1401707):

 static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
     const struct MemmapEntry *memmap = sifive_e_memmap;
+    Error *err = NULL;

     SiFiveESoCState *s = RISCV_E_SOC(dev);
     MemoryRegion *sys_mem = get_system_memory();
@@ -184,8 +188,28 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, 
Error **errp)
     sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon",
         memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
-    sifive_mmio_emulate(sys_mem, "riscv.sifive.e.gpio0",
-        memmap[SIFIVE_E_GPIO0].base, memmap[SIFIVE_E_GPIO0].size);
+    /* GPIO */
+    object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }

This function allocated xip_mem and mask_rom via g_new() but
then this error-exit doesn't free them.

The best way to fix this is to stop doing separate memory
allocations at all -- instead just have fields in the
SiFiveESoCState struct
   MemoryRegion xip_mem;
   Memory_Region mask_rom;

and pass &s->xip_mem etc where currently the code uses xip_mem.

Sorry this took a while to fix, I've just sent a patch to fix the memory leak.

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