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[Qemu-riscv] [PATCH v1 03/27] target/riscv: Add the virtulisation mode
From: |
Alistair Francis |
Subject: |
[Qemu-riscv] [PATCH v1 03/27] target/riscv: Add the virtulisation mode |
Date: |
Fri, 7 Jun 2019 14:55:27 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu.h | 4 ++++
target/riscv/cpu_bits.h | 6 ++++++
target/riscv/cpu_helper.c | 23 +++++++++++++++++++++++
3 files changed, 33 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 3337d1aef3..de4843b879 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -132,6 +132,8 @@ struct CPURISCVState {
#ifndef CONFIG_USER_ONLY
target_ulong priv;
+ /* This contains QEMU specific information about the virt state. */
+ target_ulong virt;
target_ulong resetvec;
target_ulong mhartid;
@@ -278,6 +280,8 @@ void riscv_cpu_do_interrupt(CPUState *cpu);
int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
+bool riscv_cpu_virt_enabled(CPURISCVState *env);
+void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index dc9d53d4be..07c95e8d2c 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -417,6 +417,12 @@
#define PRV_H 2 /* Reserved */
#define PRV_M 3
+/* Virtulisation modes */
+#define VIRT_OFF 0
+#define VIRT_ON 1
+#define VIRT_MODE_SHIFT 0
+#define VIRT_MODE_MASK (1 << VIRT_MODE_SHIFT)
+
/* RV32 satp CSR field masks */
#define SATP32_MODE 0x80000000
#define SATP32_ASID 0x7fc00000
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 872835177a..5912ae63b7 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -71,6 +71,29 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
#if !defined(CONFIG_USER_ONLY)
+bool riscv_cpu_virt_enabled(CPURISCVState *env)
+{
+ bool tmp;
+
+ if (!riscv_has_ext(env, RVH)) {
+ return false;
+ }
+
+ tmp = (env->virt & VIRT_MODE_MASK) >> VIRT_MODE_SHIFT;
+
+ return tmp == VIRT_ON;
+}
+
+void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
+{
+ if (!riscv_has_ext(env, RVH)) {
+ return;
+ }
+
+ env->virt &= ~VIRT_MODE_MASK;
+ env->virt |= enable << VIRT_MODE_SHIFT;
+}
+
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
{
CPURISCVState *env = &cpu->env;
--
2.21.0
- [Qemu-riscv] [PATCH v1 00/27] Add RISC-V Hypervisor Extension, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 02/27] target/riscv: Add the Hypervisor extension, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 05/27] target/riscv: Add the Hypervisor CSRs to CPUState, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 03/27] target/riscv: Add the virtulisation mode,
Alistair Francis <=
- [Qemu-riscv] [PATCH v1 01/27] target/riscv: Don't set write permissions on dirty PTEs, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 07/27] target/riscv: Remove strict perm checking for CSR R/W, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 04/27] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 06/27] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 08/27] target/riscv: Create function to test if FP is enabled, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 09/27] target/riscv: Add support for background interrupt setting, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 10/27] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 12/27] target/riscv: Add background register swapping function, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 13/27] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 16/27] riscv: plic: Always set sip.SEIP bit for HS, Alistair Francis, 2019/06/07