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[Qemu-riscv] [PULL 29/29] target/riscv: Only flush TLB if SATP.ASID chan
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From: |
Palmer Dabbelt |
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Subject: |
[Qemu-riscv] [PULL 29/29] target/riscv: Only flush TLB if SATP.ASID changes |
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Date: |
Sat, 25 May 2019 18:09:48 -0700 |
From: Jonathan Behrens <address@hidden>
There is an analogous change for ARM here:
https://patchwork.kernel.org/patch/10649857
Signed-off-by: Jonathan Behrens <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/csr.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 0f51c7eae241..f9e2910643f8 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -723,7 +723,9 @@ static int write_satp(CPURISCVState *env, int csrno,
target_ulong val)
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
return -1;
} else {
- tlb_flush(CPU(riscv_env_get_cpu(env)));
+ if((val ^ env->satp) & SATP_ASID) {
+ tlb_flush(CPU(riscv_env_get_cpu(env)));
+ }
env->satp = val;
}
}
--
2.21.0
- [Qemu-riscv] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 1, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 28/29] target/riscv: More accurate handling of `sip` CSR, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 29/29] target/riscv: Only flush TLB if SATP.ASID changes,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 27/29] target/riscv: Add checks for several RVC reserved operands, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 25/29] target/riscv: Add the HSTATUS register masks, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 26/29] target/riscv: Add the HGATP register masks, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 24/29] target/riscv: Add Hypervisor CSR macros, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 20/29] target/riscv: Trigger interrupt on MIP update asynchronously, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 23/29] target/riscv: Allow setting mstatus virtulisation bits, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 17/29] target/riscv: Deprecate the generic no MMU CPUs, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 16/29] target/riscv: Add a base 32 and 64 bit CPU, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 15/29] target/riscv: Create settable CPU properties, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 11/29] target/riscv: Remove spaces from register names, Palmer Dabbelt, 2019/05/25