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Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1 v3 6/6] riscv: Add a generi
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From: |
Alistair Francis |
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Subject: |
Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1 v3 6/6] riscv: Add a generic spike machine |
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Date: |
Thu, 11 Apr 2019 13:35:49 -0700 |
On Thu, Apr 11, 2019 at 5:18 AM Peter Maydell <address@hidden> wrote:
>
> On Thu, 11 Apr 2019 at 13:07, Igor Mammedov <address@hidden> wrote:
> >
> > On Wed, 10 Apr 2019 23:11:00 +0000
> > Alistair Francis <address@hidden> wrote:
> > > + /* register system main memory (actual RAM) */
> > > + memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
> > > + machine->ram_size, &error_fatal);
> > do you really care about migration? if not then _nomigrate flavor would
> > be more suitable.
>
> Every machine model should care about migration, at least to
> the extent of making savevm/loadvm snapshots work. Using
> memory_region_init_ram_nomigrate() is a bad idea in new
> code: it exists only for the benefit of older code which
> is handling the migration of the backing RAM by hand for
> migration-compatibility reasons.
Ok, I'll leave this as is then.
>
> > > /* Initialize SOC */
> > > object_initialize_child(OBJECT(machine), "soc", &s->soc,
> > > sizeof(s->soc),
> > > TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
> > > @@ -254,6 +343,12 @@ static void spike_v1_09_1_board_init(MachineState
> > > *machine)
> > > MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
> > > int i;
> > >
> > > + if (!qtest_enabled()) {
> > > + info_report("The Spike v1.09.1 machine has been depreceated. "
> > > + "Please use the deneric spike machine and specify
> > > the ISA "
>
> "generic"
Fixed in v4.
Alistair
>
> > > + "versions using -cpu.");
> > > + }
> > > +
>
> thanks
> -- PMM
[Qemu-riscv] [PATCH for 4.1 v3 3/6] target/riscv: Create settable CPU properties, Alistair Francis, 2019/04/10
[Qemu-riscv] [PATCH for 4.1 v3 1/6] linux-user/riscv: Add the CPU type as a comment, Alistair Francis, 2019/04/10
[Qemu-riscv] [PATCH for 4.1 v3 4/6] riscv: virt: Allow specifying a CPU via commandline, Alistair Francis, 2019/04/10
[Qemu-riscv] [PATCH for 4.1 v3 5/6] target/riscv: Remove the generic no MMU CPUs, Alistair Francis, 2019/04/10
[Qemu-riscv] [PATCH for 4.1 v3 2/6] target/riscv: Fall back to generating a RISC-V CPU, Alistair Francis, 2019/04/10