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[Qemu-riscv] [PATCH v2 11/11] riscv: sifive_u: Allow up to 4 CPUs to be
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From: |
Alistair Francis |
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Subject: |
[Qemu-riscv] [PATCH v2 11/11] riscv: sifive_u: Allow up to 4 CPUs to be created |
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Date: |
Thu, 21 Feb 2019 00:44:58 +0000 |
Signed-off-by: Alistair Francis <address@hidden>
---
hw/riscv/sifive_u.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 7bc25820fe..3199238ba0 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -398,7 +398,10 @@ static void riscv_sifive_u_machine_init(MachineClass *mc)
{
mc->desc = "RISC-V Board compatible with SiFive U SDK";
mc->init = riscv_sifive_u_init;
- mc->max_cpus = 1;
+ /* The real hardware has 5 CPUs, but one of them is a small embedded power
+ * management CPU.
+ */
+ mc->max_cpus = 4;
}
DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
--
2.20.1
- [Qemu-riscv] [PATCH v2 00/11] Upstream RISC-V fork patches, part 4, Alistair Francis, 2019/02/20
- [Qemu-riscv] [PATCH v2 02/11] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC, Alistair Francis, 2019/02/20
- [Qemu-riscv] [PATCH v2 03/11] RISC-V: Allow interrupt controllers to claim interrupts, Alistair Francis, 2019/02/20
- [Qemu-riscv] [PATCH v2 05/11] elf: Add RISC-V PSABI ELF header defines, Alistair Francis, 2019/02/20
- [Qemu-riscv] [PATCH v2 01/11] riscv: pmp: Log pmp access errors as guest errors, Alistair Francis, 2019/02/20
- [Qemu-riscv] [PATCH v2 04/11] RISC-V: Remove unnecessary disassembler constraints, Alistair Francis, 2019/02/20
- [Qemu-riscv] [PATCH v2 06/11] RISC-V: linux-user support for RVE ABI, Alistair Francis, 2019/02/20
- [Qemu-riscv] [PATCH v2 07/11] RISC-V: Change local interrupts from edge to level, Alistair Francis, 2019/02/20
- [Qemu-riscv] [PATCH v2 10/11] RISC-V: Update load reservation comment in do_interrupt, Alistair Francis, 2019/02/20
- [Qemu-riscv] [PATCH v2 11/11] riscv: sifive_u: Allow up to 4 CPUs to be created,
Alistair Francis <=
- [Qemu-riscv] [PATCH v2 09/11] RISC-V: Convert trap debugging to trace events, Alistair Francis, 2019/02/20
- [Qemu-riscv] [PATCH v2 08/11] RISC-V: Add support for vectored interrupts, Alistair Francis, 2019/02/20