Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 0/8] Upstream RISC-V fork patches, part 3

[Palmer Dabbelt]

On Mon, 14 Jan 2019 15:57:41 PST (-0800), Alistair Francis wrote:
> Alistair Francis (1):
>   RISC-V: Add priv_ver to DisasContext
>
> Michael Clark (5):
>   RISC-V: Implement mstatus.TSR/TW/TVM
>   RISC-V: Use riscv prefix consistently on cpu helpers
>   RISC-V: Add misa to DisasContext
>   RISC-V: Add misa.MAFD checks to translate
>   RISC-V: Add misa runtime write support
>
> Richard Henderson (2):
>   RISC-V: Split out mstatus_fs from tb_flags
>   RISC-V: Mark mstatus.fs dirty
>
>  linux-user/riscv/signal.c |   4 +-
>  target/riscv/cpu.c        |   2 +-
>  target/riscv/cpu.h        |  31 ++--
>  target/riscv/cpu_bits.h   |  11 ++
>  target/riscv/cpu_helper.c |  10 +-
>  target/riscv/csr.c        |  91 +++++++++---
>  target/riscv/fpu_helper.c |   6 +-
>  target/riscv/op_helper.c  |  47 ++++--
>  target/riscv/translate.c  | 292 ++++++++++++++++++++++++++++++++------
>  9 files changed, 388 insertions(+), 106 deletions(-)

Thanks.  Assuming that squash is OK I'll include these in my next PR, otherwise 
just send me a v2 and I'll swap them out.