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Re: [Qemu-riscv] [PATCH v5 24/35] target/riscv: Move gen_arith_imm() dec
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-riscv] [PATCH v5 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions |
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Date: |
Tue, 22 Jan 2019 13:36:20 -0800 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 |
On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
> gen_arith_imm() does a lot of decoding manually, which was hard to read
> in case of the shift instructions and is not necessary anymore with
> decodetree.
>
> Signed-off-by: Bastian Koppelmann <address@hidden>
> Signed-off-by: Peer Adelt <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
> + if (a->shamt >= TARGET_LONG_BITS) {
> + return false;
> + }
Watch the funky indentation.
> + if (a->rd != 0) {
> + TCGv t = tcg_temp_new();
> + gen_get_gpr(t, a->rs1);
> +
> + tcg_gen_sari_tl(t, t, a->shamt);
> + gen_set_gpr(a->rd, t);
Likewise.
r~
- [Qemu-riscv] [PATCH v5 00/35] target/riscv: Convert to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 28/35] target/riscv: Rename trans_arith to gen_arith, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 30/35] target/riscv: Remove decode_RV32_64G(), Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 31/35] target/riscv: Convert @cs_2 insns to share translation functions, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 29/35] target/riscv: Remove gen_system(), Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Bastian Koppelmann, 2019/01/22
- Re: [Qemu-riscv] [PATCH v5 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions,
Richard Henderson <=
- [Qemu-riscv] [PATCH v5 21/35] target/riscv: Remove manual decoding from gen_branch(), Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 27/35] target/riscv: Remove manual decoding of RV32/64M insn, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 13/35] target/riscv: Convert RV64F insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 26/35] target/riscv: Remove shift and slt insn manual decoding, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 22/35] target/riscv: Remove manual decoding from gen_load(), Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 23/35] target/riscv: Remove manual decoding from gen_store(), Bastian Koppelmann, 2019/01/22