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Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u:
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From: |
Alistair Francis |
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Subject: |
Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe |
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Date: |
Wed, 21 Nov 2018 18:23:26 -0800 |
On Wed, Nov 21, 2018 at 6:13 PM Palmer Dabbelt <address@hidden> wrote:
>
> On Wed, 21 Nov 2018 15:26:01 PST (-0800), address@hidden wrote:
> >
> >
> > On 2018-11-21 4:10 p.m., Guenter Roeck wrote:
> >> FWIW, I absoutely agree. If the board can only be used to boot an initrd,
> >> it is quite pointless to have it around. Actually it is worse than
> >> pointless,
> >> since it will result in people wasting their time trying to get it to work.
> >
> > As someone who has wasted their time on it, I second this sentiment.
>
> So it sounds like I should target that deprecation patch set for 3.1? Who
> wants to review it?
I think it's a little late for 3.1. Let's leave it for 3.2
Alistair
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, (continued)
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Palmer Dabbelt, 2018/11/21
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Palmer Dabbelt, 2018/11/21
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Palmer Dabbelt, 2018/11/21
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Guenter Roeck, 2018/11/21
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Palmer Dabbelt, 2018/11/21
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe,
Alistair Francis <=
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Palmer Dabbelt, 2018/11/26
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Guenter Roeck, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Logan Gunthorpe, 2018/11/21
[Qemu-riscv] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device, Alistair Francis, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device, Logan Gunthorpe, 2018/11/21
- Re: [Qemu-riscv] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device, Alistair Francis, 2018/11/21