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Re: [Qemu-riscv] [PATCH v3 25/35] target/riscv: make ADD/SUB/OR/XOR/AND
From: |
Richard Henderson |
Subject: |
Re: [Qemu-riscv] [PATCH v3 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists |
Date: |
Wed, 31 Oct 2018 22:26:37 +0000 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 |
On 10/31/18 1:20 PM, Bastian Koppelmann wrote:
> static bool trans_addw(DisasContext *ctx, arg_addw *a)
> {
> - gen_arith(ctx, OPC_RISC_ADDW, a->rd, a->rs1, a->rs2);
> - return true;
> + return trans_arith(ctx, a, &tcg_gen_add_tl);
> }
This should be using gen_addw.
r~
- [Qemu-riscv] [PATCH v3 04/35] target/riscv: Convert RV32I load/store insns to decodetree, (continued)
- [Qemu-riscv] [PATCH v3 04/35] target/riscv: Convert RV32I load/store insns to decodetree, Bastian Koppelmann, 2018/10/31
- [Qemu-riscv] [PATCH v3 06/35] target/riscv: Convert RVXI arithmetic insns to decodetree, Bastian Koppelmann, 2018/10/31
- [Qemu-riscv] [PATCH v3 12/35] target/riscv: Convert RV32F insns to decodetree, Bastian Koppelmann, 2018/10/31
- [Qemu-riscv] [PATCH v3 08/35] target/riscv: Convert RVXI csr insns to decodetree, Bastian Koppelmann, 2018/10/31
- [Qemu-riscv] [PATCH v3 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Bastian Koppelmann, 2018/10/31
- [Qemu-riscv] [PATCH v3 21/35] target/riscv: Remove manual decoding from gen_branch(), Bastian Koppelmann, 2018/10/31
- [Qemu-riscv] [PATCH v3 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64, Bastian Koppelmann, 2018/10/31
- [Qemu-riscv] [PATCH v3 23/35] target/riscv: Remove manual decoding from gen_store(), Bastian Koppelmann, 2018/10/31
- [Qemu-riscv] [PATCH v3 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Bastian Koppelmann, 2018/10/31
- [Qemu-riscv] [PATCH v3 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64, Bastian Koppelmann, 2018/10/31