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[PATCH 2/6] ppc/pnv: raise no-response errors if an LPC transaction fail
From: |
Nicholas Piggin |
Subject: |
[PATCH 2/6] ppc/pnv: raise no-response errors if an LPC transaction fails |
Date: |
Mon, 3 Mar 2025 20:33:53 +1000 |
If nothing responds to an LPC access, the LPC host controller should
set an IRQSTAT error. Model this behaviour.
skiboot uses this error to "probe" LPC accesses, among other things to
determine if a SuperIO chip is present. After this change it recognizes
there is no SuperIO present and does not keep trying to access it.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/pnv_lpc.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index d0fccc165d9..0e02ce6e940 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv_lpc.c
@@ -353,6 +353,8 @@ static const MemoryRegionOps pnv_lpc_xscom_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
+static void pnv_lpc_opb_noresponse(PnvLpcController *lpc);
+
static uint64_t pnv_lpc_mmio_read(void *opaque, hwaddr addr, unsigned size)
{
PnvLpcController *lpc = PNV_LPC(opaque);
@@ -376,6 +378,7 @@ static uint64_t pnv_lpc_mmio_read(void *opaque, hwaddr
addr, unsigned size)
}
if (result != MEMTX_OK) {
+ pnv_lpc_opb_noresponse(lpc);
qemu_log_mask(LOG_GUEST_ERROR, "OPB read failed at @0x%"
HWADDR_PRIx "\n", addr);
}
@@ -406,6 +409,7 @@ static void pnv_lpc_mmio_write(void *opaque, hwaddr addr,
}
if (result != MEMTX_OK) {
+ pnv_lpc_opb_noresponse(lpc);
qemu_log_mask(LOG_GUEST_ERROR, "OPB write failed at @0x%"
HWADDR_PRIx "\n", addr);
}
@@ -511,6 +515,12 @@ static void pnv_lpc_eval_irqs(PnvLpcController *lpc)
qemu_set_irq(lpc->psi_irq_lpchc, lpc->opb_irq_stat != 0);
}
+static void pnv_lpc_opb_noresponse(PnvLpcController *lpc)
+{
+ lpc->lpc_hc_irqstat |= LPC_HC_IRQ_SYNC_NORESP_ERR;
+ pnv_lpc_eval_irqs(lpc);
+}
+
static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size)
{
PnvLpcController *lpc = opaque;
--
2.47.1
- [PATCH 0/6] ppc/pnv: LPC fixes and add nice PNOR image, Nicholas Piggin, 2025/03/03
- [PATCH 2/6] ppc/pnv: raise no-response errors if an LPC transaction fails,
Nicholas Piggin <=
- [PATCH 4/6] ppc/pnv: Move PNOR to offset 0 in the ISA FW space, Nicholas Piggin, 2025/03/03
- [PATCH 1/6] ppc/pnv: Support LPC host controller irqs other than serirqs, Nicholas Piggin, 2025/03/03
- [PATCH 3/6] ppc/pnv: Implement LPC FW address space IDSEL, Nicholas Piggin, 2025/03/03
- [PATCH 5/6] ppc/pnv: Add a PNOR address and size sanity checks, Nicholas Piggin, 2025/03/03
- [PATCH 6/6] ppc/pnv: Add a default formatted PNOR image, Nicholas Piggin, 2025/03/03