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[PATCH v5 06/29] e1000e: Mask registers when writing
From: |
Akihiko Odaki |
Subject: |
[PATCH v5 06/29] e1000e: Mask registers when writing |
Date: |
Wed, 1 Feb 2023 12:35:16 +0900 |
When a register has effective bits fewer than their width, the old code
inconsistently masked when writing or reading. Make the code consistent
by always masking when writing, and remove some code duplication.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
---
hw/net/e1000e_core.c | 94 +++++++++++++++++++-------------------------
1 file changed, 40 insertions(+), 54 deletions(-)
diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c
index 181c1e0c2a..e6fc85ea51 100644
--- a/hw/net/e1000e_core.c
+++ b/hw/net/e1000e_core.c
@@ -2440,17 +2440,19 @@ e1000e_set_fcrtl(E1000ECore *core, int index, uint32_t
val)
core->mac[FCRTL] = val & 0x8000FFF8;
}
-static inline void
-e1000e_set_16bit(E1000ECore *core, int index, uint32_t val)
-{
- core->mac[index] = val & 0xffff;
-}
+#define E1000E_LOW_BITS_SET_FUNC(num) \
+ static void \
+ e1000e_set_##num##bit(E1000ECore *core, int index, uint32_t val) \
+ { \
+ core->mac[index] = val & (BIT(num) - 1); \
+ }
-static void
-e1000e_set_12bit(E1000ECore *core, int index, uint32_t val)
-{
- core->mac[index] = val & 0xfff;
-}
+E1000E_LOW_BITS_SET_FUNC(4)
+E1000E_LOW_BITS_SET_FUNC(6)
+E1000E_LOW_BITS_SET_FUNC(11)
+E1000E_LOW_BITS_SET_FUNC(12)
+E1000E_LOW_BITS_SET_FUNC(13)
+E1000E_LOW_BITS_SET_FUNC(16)
static void
e1000e_set_vet(E1000ECore *core, int index, uint32_t val)
@@ -2621,22 +2623,6 @@ e1000e_mac_ims_read(E1000ECore *core, int index)
return core->mac[IMS];
}
-#define E1000E_LOW_BITS_READ_FUNC(num) \
- static uint32_t \
- e1000e_mac_low##num##_read(E1000ECore *core, int index) \
- { \
- return core->mac[index] & (BIT(num) - 1); \
- } \
-
-#define E1000E_LOW_BITS_READ(num) \
- e1000e_mac_low##num##_read
-
-E1000E_LOW_BITS_READ_FUNC(4);
-E1000E_LOW_BITS_READ_FUNC(6);
-E1000E_LOW_BITS_READ_FUNC(11);
-E1000E_LOW_BITS_READ_FUNC(13);
-E1000E_LOW_BITS_READ_FUNC(16);
-
static uint32_t
e1000e_mac_swsm_read(E1000ECore *core, int index)
{
@@ -2930,7 +2916,19 @@ static const readops e1000e_macreg_readops[] = {
e1000e_getreg(LATECOL),
e1000e_getreg(SEQEC),
e1000e_getreg(XONTXC),
+ e1000e_getreg(AIT),
+ e1000e_getreg(TDFH),
+ e1000e_getreg(TDFT),
+ e1000e_getreg(TDFHS),
+ e1000e_getreg(TDFTS),
+ e1000e_getreg(TDFPC),
e1000e_getreg(WUS),
+ e1000e_getreg(PBS),
+ e1000e_getreg(RDFH),
+ e1000e_getreg(RDFT),
+ e1000e_getreg(RDFHS),
+ e1000e_getreg(RDFTS),
+ e1000e_getreg(RDFPC),
e1000e_getreg(GORCL),
e1000e_getreg(MGTPRC),
e1000e_getreg(EERD),
@@ -3066,16 +3064,9 @@ static const readops e1000e_macreg_readops[] = {
[MPTC] = e1000e_mac_read_clr4,
[IAC] = e1000e_mac_read_clr4,
[ICR] = e1000e_mac_icr_read,
- [RDFH] = E1000E_LOW_BITS_READ(13),
- [RDFHS] = E1000E_LOW_BITS_READ(13),
- [RDFPC] = E1000E_LOW_BITS_READ(13),
- [TDFH] = E1000E_LOW_BITS_READ(13),
- [TDFHS] = E1000E_LOW_BITS_READ(13),
[STATUS] = e1000e_get_status,
[TARC0] = e1000e_get_tarc,
- [PBS] = E1000E_LOW_BITS_READ(6),
[ICS] = e1000e_mac_ics_read,
- [AIT] = E1000E_LOW_BITS_READ(16),
[TORH] = e1000e_mac_read_clr8,
[GORCH] = e1000e_mac_read_clr8,
[PRC127] = e1000e_mac_read_clr4,
@@ -3091,11 +3082,6 @@ static const readops e1000e_macreg_readops[] = {
[BPTC] = e1000e_mac_read_clr4,
[TSCTC] = e1000e_mac_read_clr4,
[ITR] = e1000e_mac_itr_read,
- [RDFT] = E1000E_LOW_BITS_READ(13),
- [RDFTS] = E1000E_LOW_BITS_READ(13),
- [TDFPC] = E1000E_LOW_BITS_READ(13),
- [TDFT] = E1000E_LOW_BITS_READ(13),
- [TDFTS] = E1000E_LOW_BITS_READ(13),
[CTRL] = e1000e_get_ctrl,
[TARC1] = e1000e_get_tarc,
[SWSM] = e1000e_mac_swsm_read,
@@ -3108,10 +3094,10 @@ static const readops e1000e_macreg_readops[] = {
[WUPM ... WUPM + 31] = e1000e_mac_readreg,
[MTA ... MTA + 127] = e1000e_mac_readreg,
[VFTA ... VFTA + 127] = e1000e_mac_readreg,
- [FFMT ... FFMT + 254] = E1000E_LOW_BITS_READ(4),
+ [FFMT ... FFMT + 254] = e1000e_mac_readreg,
[FFVT ... FFVT + 254] = e1000e_mac_readreg,
[MDEF ... MDEF + 7] = e1000e_mac_readreg,
- [FFLT ... FFLT + 10] = E1000E_LOW_BITS_READ(11),
+ [FFLT ... FFLT + 10] = e1000e_mac_readreg,
[FTFT ... FTFT + 254] = e1000e_mac_readreg,
[PBM ... PBM + 10239] = e1000e_mac_readreg,
[RETA ... RETA + 31] = e1000e_mac_readreg,
@@ -3134,19 +3120,8 @@ static const writeops e1000e_macreg_writeops[] = {
e1000e_putreg(LEDCTL),
e1000e_putreg(FCAL),
e1000e_putreg(FCRUC),
- e1000e_putreg(AIT),
- e1000e_putreg(TDFH),
- e1000e_putreg(TDFT),
- e1000e_putreg(TDFHS),
- e1000e_putreg(TDFTS),
- e1000e_putreg(TDFPC),
e1000e_putreg(WUC),
e1000e_putreg(WUS),
- e1000e_putreg(RDFH),
- e1000e_putreg(RDFT),
- e1000e_putreg(RDFHS),
- e1000e_putreg(RDFTS),
- e1000e_putreg(RDFPC),
e1000e_putreg(IPAV),
e1000e_putreg(TDBAH1),
e1000e_putreg(TIMINCA),
@@ -3157,7 +3132,6 @@ static const writeops e1000e_macreg_writeops[] = {
e1000e_putreg(TARC1),
e1000e_putreg(FLSWDATA),
e1000e_putreg(POEMB),
- e1000e_putreg(PBS),
e1000e_putreg(MFUTP01),
e1000e_putreg(MFUTP23),
e1000e_putreg(MANC),
@@ -3222,6 +3196,18 @@ static const writeops e1000e_macreg_writeops[] = {
[TADV] = e1000e_set_16bit,
[ITR] = e1000e_set_itr,
[EERD] = e1000e_set_eerd,
+ [AIT] = e1000e_set_16bit,
+ [TDFH] = e1000e_set_13bit,
+ [TDFT] = e1000e_set_13bit,
+ [TDFHS] = e1000e_set_13bit,
+ [TDFTS] = e1000e_set_13bit,
+ [TDFPC] = e1000e_set_13bit,
+ [RDFH] = e1000e_set_13bit,
+ [RDFHS] = e1000e_set_13bit,
+ [RDFT] = e1000e_set_13bit,
+ [RDFTS] = e1000e_set_13bit,
+ [RDFPC] = e1000e_set_13bit,
+ [PBS] = e1000e_set_6bit,
[GCR] = e1000e_set_gcr,
[PSRCTL] = e1000e_set_psrctl,
[RXCSUM] = e1000e_set_rxcsum,
@@ -3261,11 +3247,11 @@ static const writeops e1000e_macreg_writeops[] = {
[WUPM ... WUPM + 31] = e1000e_mac_writereg,
[MTA ... MTA + 127] = e1000e_mac_writereg,
[VFTA ... VFTA + 127] = e1000e_mac_writereg,
- [FFMT ... FFMT + 254] = e1000e_mac_writereg,
+ [FFMT ... FFMT + 254] = e1000e_set_4bit,
[FFVT ... FFVT + 254] = e1000e_mac_writereg,
[PBM ... PBM + 10239] = e1000e_mac_writereg,
[MDEF ... MDEF + 7] = e1000e_mac_writereg,
- [FFLT ... FFLT + 10] = e1000e_mac_writereg,
+ [FFLT ... FFLT + 10] = e1000e_set_11bit,
[FTFT ... FTFT + 254] = e1000e_mac_writereg,
[RETA ... RETA + 31] = e1000e_mac_writereg,
[RSSRK ... RSSRK + 31] = e1000e_mac_writereg,
--
2.39.1
- [PATCH v5 00/29] e1000x cleanups (preliminary for IGB), Akihiko Odaki, 2023/01/31
- [PATCH v5 01/29] e1000e: Fix the code style, Akihiko Odaki, 2023/01/31
- [PATCH v5 03/29] fsl_etsec: Use hw/net/mii.h, Akihiko Odaki, 2023/01/31
- [PATCH v5 04/29] e1000: Use hw/net/mii.h, Akihiko Odaki, 2023/01/31
- [PATCH v5 02/29] hw/net: Add more MII definitions, Akihiko Odaki, 2023/01/31
- [PATCH v5 06/29] e1000e: Mask registers when writing,
Akihiko Odaki <=
- [PATCH v5 07/29] e1000: Use more constant definitions, Akihiko Odaki, 2023/01/31
- [PATCH v5 08/29] e1000e: Use more constant definitions, Akihiko Odaki, 2023/01/31
- [PATCH v5 09/29] e1000: Use memcpy to intialize registers, Akihiko Odaki, 2023/01/31
- [PATCH v5 05/29] e1000: Mask registers when writing, Akihiko Odaki, 2023/01/31
- [PATCH v5 10/29] e1000e: Use memcpy to intialize registers, Akihiko Odaki, 2023/01/31
- [PATCH v5 11/29] e1000e: Remove pending interrupt flags, Akihiko Odaki, 2023/01/31
- [PATCH v5 12/29] e1000e: Improve software reset, Akihiko Odaki, 2023/01/31
- [PATCH v5 13/29] e1000: Configure ResettableClass, Akihiko Odaki, 2023/01/31
- [PATCH v5 14/29] e1000e: Configure ResettableClass, Akihiko Odaki, 2023/01/31
- [PATCH v5 15/29] e1000e: Introduce e1000_rx_desc_union, Akihiko Odaki, 2023/01/31