Re: [PATCH] target/ppc: Fix BookE debug interrupt generation

[Bin Meng]

On Wed, Apr 20, 2022 at 9:50 PM Fabiano Rosas <farosas@linux.ibm.com> wrote:
>
> Bin Meng <bmeng.cn@gmail.com> writes:
>
> > From: Bin Meng <bin.meng@windriver.com>
> >
> > Per PowerISA v2.07 [1], Book III-E, chapter 7.6 "Interrupt definitions"
>
> Which BookE board are you concerned about? I don't think we have any
> BookE ISA v2.07 in QEMU currently.

It's actually a PPC E500 core, but I am too lazy to dig out the E500
manual from Freescale/NXP :(

Let me know if I need to replace the link to an E500 manual.

>
> > "When in Internal Debug Mode with MSR.DE=0, then Instruction Complete
> > and Branch Taken debug events cannot occur, and no DBSR status bits
> > are set and no subsequent imprecise Debug interrupt will occur."
> >
> > Current codes do not check MSR.DE bit before setting HFLAGS_SE and
> > HFLAGS_BE flag, which would cause the immediate debug interrupt to
> > be generated, e.g.: when DBCR0.ICMP bit is set by guest software
> > and MSR.DE is not set.
> >
>
> The rationale and the change itself look ok.
>
> > [1] https://ibm.ent.box.com/s/jd5w15gz301s5b5dt375mshpq9c3lh4u
> >
> > Signed-off-by: Bin Meng <bin.meng@windriver.com>
> > ---
> >
> >  target/ppc/helper_regs.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >

Regards,
Bin