include/hw/ppc/xive.h | 1 +
hw/intc/xive.c | 9 +++++++++
hw/intc/xive2.c | 10 ++++++++++
3 files changed, 20 insertions(+)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index b8ab0bf7490f..875c7f639689 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -278,6 +278,7 @@ uint8_t xive_esb_set(uint8_t *pq, uint8_t value);
#define XIVE_ESB_STORE_EOI 0x400 /* Store */
#define XIVE_ESB_LOAD_EOI 0x000 /* Load */
#define XIVE_ESB_GET 0x800 /* Load */
+#define XIVE_ESB_INJECT 0x800 /* Store */
#define XIVE_ESB_SET_PQ_00 0xc00 /* Load */
#define XIVE_ESB_SET_PQ_01 0xd00 /* Load */
#define XIVE_ESB_SET_PQ_10 0xe00 /* Load */
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 190194d27f84..2c73ab5ca9d6 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1061,6 +1061,15 @@ static void xive_source_esb_write(void *opaque, hwaddr
addr,
notify = xive_source_esb_eoi(xsrc, srcno);
break;
+ /*
+ * This is an internal offset used to inject triggers when the PQ
+ * state bits are not controlled locally. Such as for LSIs when
+ * under ABT mode.
+ */
+ case XIVE_ESB_INJECT ... XIVE_ESB_INJECT + 0x3FF:
+ notify = true;
+ break;
+
case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF:
case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF:
case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF:
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index 9e186bbb6cd9..d474476b5a55 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -658,6 +658,16 @@ static void xive2_end_source_write(void *opaque, hwaddr
addr,
notify = xive_esb_eoi(&pq);
break;
+ case XIVE_ESB_INJECT ... XIVE_ESB_INJECT + 0x3FF:
+ if (end_esmask == END2_W1_ESe) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "XIVE: END %x/%x can not EQ inject on ESe\n",
+ end_blk, end_idx);
+ return;
+ }
+ notify = true;
+ break;
+
default:
qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB write addr
%d\n",
offset);