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[PATCH v4 20/47] target/ppc: implement vslq
From: |
matheus . ferst |
Subject: |
[PATCH v4 20/47] target/ppc: implement vslq |
Date: |
Tue, 22 Feb 2022 11:36:18 -0300 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v4:
- New in v4.
---
target/ppc/insn32.decode | 1 +
target/ppc/translate/vmx-impl.c.inc | 40 +++++++++++++++++++++++++++++
2 files changed, 41 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 88baebe35e..3799065508 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -473,6 +473,7 @@ VSLB 000100 ..... ..... ..... 00100000100 @VX
VSLH 000100 ..... ..... ..... 00101000100 @VX
VSLW 000100 ..... ..... ..... 00110000100 @VX
VSLD 000100 ..... ..... ..... 10111000100 @VX
+VSLQ 000100 ..... ..... ..... 00100000101 @VX
VSRB 000100 ..... ..... ..... 01000000100 @VX
VSRH 000100 ..... ..... ..... 01001000100 @VX
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index ec4f0e7654..ca98a545ef 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -834,6 +834,46 @@ TRANS_FLAGS(ALTIVEC, VSRAH, do_vector_gvec3_VX, MO_16,
tcg_gen_gvec_sarv);
TRANS_FLAGS(ALTIVEC, VSRAW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_sarv);
TRANS_FLAGS2(ALTIVEC_207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sarv);
+static bool trans_VSLQ(DisasContext *ctx, arg_VX *a)
+{
+ TCGv_i64 hi, lo, tmp, n, sf = tcg_constant_i64(64);
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ n = tcg_temp_new_i64();
+ hi = tcg_temp_new_i64();
+ lo = tcg_temp_new_i64();
+ tmp = tcg_const_i64(0);
+
+ get_avr64(lo, a->vra, false);
+ get_avr64(hi, a->vra, true);
+
+ get_avr64(n, a->vrb, true);
+ tcg_gen_andi_i64(n, n, 0x7F);
+
+ tcg_gen_movcond_i64(TCG_COND_GE, hi, n, sf, lo, hi);
+ tcg_gen_movcond_i64(TCG_COND_GE, lo, n, sf, tmp, lo);
+ tcg_gen_andi_i64(n, n, ~64ULL);
+
+ tcg_gen_shl_i64(tmp, lo, n);
+ set_avr64(a->vrt, tmp, false);
+
+ tcg_gen_shl_i64(hi, hi, n);
+ tcg_gen_xori_i64(n, n, 63);
+ tcg_gen_shr_i64(lo, lo, n);
+ tcg_gen_shri_i64(lo, lo, 1);
+ tcg_gen_or_i64(hi, hi, lo);
+ set_avr64(a->vrt, hi, true);
+
+ tcg_temp_free_i64(hi);
+ tcg_temp_free_i64(lo);
+ tcg_temp_free_i64(tmp);
+ tcg_temp_free_i64(n);
+
+ return true;
+}
+
#define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \
static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \
TCGv_vec sat, TCGv_vec a, \
--
2.25.1
- Re: [PATCH v4 11/47] target/ppc: Implement Vector Compare Equal Quadword, (continued)
- [PATCH v4 13/47] target/ppc: Implement Vector Compare Quadword, matheus . ferst, 2022/02/22
- [PATCH v4 14/47] target/ppc: implement vstri[bh][lr], matheus . ferst, 2022/02/22
- [PATCH v4 15/47] target/ppc: implement vclrlb, matheus . ferst, 2022/02/22
- [PATCH v4 16/47] target/ppc: implement vclrrb, matheus . ferst, 2022/02/22
- [PATCH v4 18/47] target/ppc: implement vgnb, matheus . ferst, 2022/02/22
- [PATCH v4 20/47] target/ppc: implement vslq,
matheus . ferst <=
- [PATCH v4 17/47] target/ppc: implement vcntmb[bhwd], matheus . ferst, 2022/02/22
- [PATCH v4 22/47] target/ppc: implement vsraq, matheus . ferst, 2022/02/22
- [PATCH v4 21/47] target/ppc: implement vsrq, matheus . ferst, 2022/02/22
- [PATCH v4 19/47] target/ppc: move vs[lr][a][bhwd] to decodetree, matheus . ferst, 2022/02/22