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[PULL 21/39] target/ppc: cpu_init: Decouple 74xx SPR registration from 7
From: |
Cédric Le Goater |
Subject: |
[PULL 21/39] target/ppc: cpu_init: Decouple 74xx SPR registration from 7xx |
Date: |
Fri, 18 Feb 2022 11:38:09 +0100 |
From: Fabiano Rosas <farosas@linux.ibm.com>
We're considering these two to be from different CPU families, so
duplicate some code to keep them separate.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-10-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 107 +++++++++++++++++++++++++++++++++++-------
1 file changed, 91 insertions(+), 16 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 36d6377a51d2..5ca0d78dd42f 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -803,6 +803,97 @@ static void register_G2_sprs(CPUPPCState *env)
static void register_74xx_sprs(CPUPPCState *env)
{
+ /* Breakpoints */
+ spr_register_kvm(env, SPR_DABR, "DABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DABR, 0x00000000);
+
+ spr_register(env, SPR_IABR, "IABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Cache management */
+ spr_register(env, SPR_ICTC, "ICTC",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Performance monitors */
+ spr_register(env, SPR_7XX_MMCR0, "MMCR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_MMCR1, "MMCR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_PMC1, "PMC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_PMC2, "PMC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_PMC3, "PMC3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_PMC4, "PMC4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_SIAR, "SIAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_UPMC1, "UPMC1",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_UPMC2, "UPMC2",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_UPMC3, "UPMC3",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_UPMC4, "UPMC4",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_USIAR, "USIAR",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* External access control */
+ spr_register(env, SPR_EAR, "EAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
/* Processor identification */
spr_register(env, SPR_PIR, "PIR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -4640,8 +4731,6 @@ static void init_proc_7400(CPUPPCState *env)
{
register_ne_601_sprs(env);
register_sdr1_sprs(env);
- register_7xx_sprs(env);
- /* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -4714,8 +4803,6 @@ static void init_proc_7410(CPUPPCState *env)
{
register_ne_601_sprs(env);
register_sdr1_sprs(env);
- register_7xx_sprs(env);
- /* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -4795,8 +4882,6 @@ static void init_proc_7440(CPUPPCState *env)
{
register_ne_601_sprs(env);
register_sdr1_sprs(env);
- register_7xx_sprs(env);
- /* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -4897,8 +4982,6 @@ static void init_proc_7450(CPUPPCState *env)
{
register_ne_601_sprs(env);
register_sdr1_sprs(env);
- register_7xx_sprs(env);
- /* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* Level 3 cache control */
@@ -5021,8 +5104,6 @@ static void init_proc_7445(CPUPPCState *env)
{
register_ne_601_sprs(env);
register_sdr1_sprs(env);
- register_7xx_sprs(env);
- /* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* LDSTCR */
@@ -5152,8 +5233,6 @@ static void init_proc_7455(CPUPPCState *env)
{
register_ne_601_sprs(env);
register_sdr1_sprs(env);
- register_7xx_sprs(env);
- /* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* Level 3 cache control */
@@ -5285,8 +5364,6 @@ static void init_proc_7457(CPUPPCState *env)
{
register_ne_601_sprs(env);
register_sdr1_sprs(env);
- register_7xx_sprs(env);
- /* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* Level 3 cache control */
@@ -5438,8 +5515,6 @@ static void init_proc_e600(CPUPPCState *env)
{
register_ne_601_sprs(env);
register_sdr1_sprs(env);
- register_7xx_sprs(env);
- /* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
--
2.34.1
- [PULL 26/39] target/ppc: cpu_init: Deduplicate 7xx SPR registration, (continued)
- [PULL 26/39] target/ppc: cpu_init: Deduplicate 7xx SPR registration, Cédric Le Goater, 2022/02/18
- [PULL 16/39] target/ppc: cpu_init: Move Timebase registration into the common function, Cédric Le Goater, 2022/02/18
- [PULL 24/39] target/ppc: cpu_init: Deduplicate 604 SPR registration, Cédric Le Goater, 2022/02/18
- [PULL 02/39] spapr: nvdimm: Implement H_SCM_FLUSH hcall, Cédric Le Goater, 2022/02/18
- [PULL 28/39] target/ppc: cpu_init: Move e300 SPR registration into a function, Cédric Le Goater, 2022/02/18
- [PULL 30/39] target/ppc: cpu_init: Reuse init_proc_603 for the e300, Cédric Le Goater, 2022/02/18
- [PULL 03/39] spapr: nvdimm: Introduce spapr-nvdimm device, Cédric Le Goater, 2022/02/18
- [PULL 11/39] target/ppc: Introduce a vhyp framework for nested HV support, Cédric Le Goater, 2022/02/18
- [PULL 34/39] target/ppc: cpu_init: Remove register_usprg3_sprs, Cédric Le Goater, 2022/02/18
- [PULL 25/39] target/ppc: cpu_init: Deduplicate 745/755 SPR registration, Cédric Le Goater, 2022/02/18
- [PULL 21/39] target/ppc: cpu_init: Decouple 74xx SPR registration from 7xx,
Cédric Le Goater <=
- [PULL 22/39] target/ppc: cpu_init: Deduplicate 440 SPR registration, Cédric Le Goater, 2022/02/18
- [PULL 36/39] target/ppc: cpu_init: Expose some SPR registration helpers, Cédric Le Goater, 2022/02/18
- [PULL 35/39] target/ppc: Rename spr_tcg.h to spr_common.h, Cédric Le Goater, 2022/02/18
- [PULL 05/39] spapr: prevent hdec timer being set up under virtual hypervisor, Cédric Le Goater, 2022/02/18
- [PULL 09/39] target/ppc: add helper for books vhyp hypercall handler, Cédric Le Goater, 2022/02/18
- [PULL 32/39] target/ppc: cpu_init: Reuse init_proc_745 for the 755, Cédric Le Goater, 2022/02/18
- [PULL 33/39] target/ppc: cpu_init: Rename register_ne_601_sprs, Cédric Le Goater, 2022/02/18
- [PULL 20/39] target/ppc: cpu_init: Decouple G2 SPR registration from 755, Cédric Le Goater, 2022/02/18
- [PULL 12/39] spapr: implement nested-hv capability for the virtual hypervisor, Cédric Le Goater, 2022/02/18
- [PULL 31/39] target/ppc: cpu_init: Reuse init_proc_604 for the 604e, Cédric Le Goater, 2022/02/18