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[PULL 24/42] target/ppc: 6xx: Software TLB exceptions cleanup
From: |
Cédric Le Goater |
Subject: |
[PULL 24/42] target/ppc: 6xx: Software TLB exceptions cleanup |
Date: |
Thu, 10 Feb 2022 13:59:50 +0100 |
From: Fabiano Rosas <farosas@linux.ibm.com>
This code applies only to the 6xx CPUs, so we can remove the switch
statement.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220203200957.1434641-11-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/excp_helper.c | 31 +++++++++++--------------------
1 file changed, 11 insertions(+), 20 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 538905c4dd55..80168355bdfa 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -553,7 +553,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
- int excp_model = env->excp_model;
target_ulong msr, new_msr, vector;
int srr0, srr1;
@@ -695,26 +694,18 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
- switch (excp_model) {
- case POWERPC_EXCP_6xx:
- /* Swap temporary saved registers with GPRs */
- if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
- new_msr |= (target_ulong)1 << MSR_TGPR;
- hreg_swap_gpr_tgpr(env);
- }
- /* fall through */
- case POWERPC_EXCP_7x5:
- ppc_excp_debug_sw_tlb(env, excp);
-
- msr |= env->crf[0] << 28;
- msr |= env->error_code; /* key, D/I, S/L bits */
- /* Set way using a LRU mechanism */
- msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
- break;
- default:
- cpu_abort(cs, "Invalid TLB miss exception\n");
- break;
+ /* Swap temporary saved registers with GPRs */
+ if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
+ new_msr |= (target_ulong)1 << MSR_TGPR;
+ hreg_swap_gpr_tgpr(env);
}
+
+ ppc_excp_debug_sw_tlb(env, excp);
+
+ msr |= env->crf[0] << 28;
+ msr |= env->error_code; /* key, D/I, S/L bits */
+ /* Set way using a LRU mechanism */
+ msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
break;
case POWERPC_EXCP_FPA: /* Floating-point assist exception */
case POWERPC_EXCP_DABR: /* Data address breakpoint */
--
2.34.1
- [PULL 23/42] target/ppc: 6xx: System Reset interrupt cleanup, (continued)
- [PULL 23/42] target/ppc: 6xx: System Reset interrupt cleanup, Cédric Le Goater, 2022/02/10
- [PULL 30/42] target/ppc: 7xx: External interrupt cleanup, Cédric Le Goater, 2022/02/10
- [PULL 39/42] target/ppc: books: Remove excp_model argument from ppc_excp_apply_ail, Cédric Le Goater, 2022/02/10
- [PULL 34/42] target/ppc: 7xx: Software TLB cleanup, Cédric Le Goater, 2022/02/10
- [PULL 05/42] target/ppc: booke: Machine Check cleanups, Cédric Le Goater, 2022/02/10
- [PULL 17/42] target/ppc: Simplify powerpc_excp_6xx, Cédric Le Goater, 2022/02/10
- [PULL 26/42] target/ppc: Merge 7x5 and 7x0 exception model IDs, Cédric Le Goater, 2022/02/10
- [PULL 13/42] target/ppc: Fix radix logging, Cédric Le Goater, 2022/02/10
- [PULL 38/42] target/ppc: Assert if MSR bits differ from msr_mask during exceptions, Cédric Le Goater, 2022/02/10
- [PULL 16/42] target/ppc: Introduce powerpc_excp_6xx, Cédric Le Goater, 2022/02/10
- [PULL 24/42] target/ppc: 6xx: Software TLB exceptions cleanup,
Cédric Le Goater <=
- [PULL 28/42] target/ppc: Simplify powerpc_excp_7xx, Cédric Le Goater, 2022/02/10
- [PULL 22/42] target/ppc: 6xx: System Call exception cleanup, Cédric Le Goater, 2022/02/10
- [PULL 33/42] target/ppc: 7xx: System Reset cleanup, Cédric Le Goater, 2022/02/10
- [PULL 35/42] target/ppc: 7xx: Set SRRs directly in exception code, Cédric Le Goater, 2022/02/10
- [PULL 27/42] target/ppc: Introduce powerpc_excp_7xx, Cédric Le Goater, 2022/02/10
- [PULL 41/42] docs: rstfy confidential guest documentation, Cédric Le Goater, 2022/02/10
- [PULL 03/42] target/ppc: Simplify powerpc_excp_booke, Cédric Le Goater, 2022/02/10
- [PULL 29/42] target/ppc: 7xx: Machine Check exception cleanup, Cédric Le Goater, 2022/02/10
- [PULL 40/42] target/ppc: Change VSX instructions behavior to fill with zeros, Cédric Le Goater, 2022/02/10
- [PULL 25/42] target/ppc: 6xx: Set SRRs directly in exception code, Cédric Le Goater, 2022/02/10