Re: [PATCH v3 2/3] test/tcg/ppc64le: test mtfsf

[Cédric Le Goater]

Hello Lucas,

On 11/24/21 18:25, Lucas Mateus Castro (alqotel) wrote:
> Added tests for the mtfsf to check if FI bit of FPSCR is being set
> and if exception calls are being made correctly.
>
> Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>

Could you please rebase on mainline and resend ?

Thanks,

C.
 
> ---
>   tests/tcg/ppc64/Makefile.target   |  1 +
>   tests/tcg/ppc64le/Makefile.target |  1 +
>   tests/tcg/ppc64le/mtfsf.c         | 61 +++++++++++++++++++++++++++++++
>   3 files changed, 63 insertions(+)
>   create mode 100644 tests/tcg/ppc64le/mtfsf.c
>
> diff --git a/tests/tcg/ppc64/Makefile.target b/tests/tcg/ppc64/Makefile.target
> index 6ab7934fdf..8f4c7ac4ed 100644
> --- a/tests/tcg/ppc64/Makefile.target
> +++ b/tests/tcg/ppc64/Makefile.target
> @@ -11,6 +11,7 @@ endif
>   bcdsub: CFLAGS += -mpower8-vector
>   
>   PPC64_TESTS += byte_reverse
> +PPC64_TESTS += mtfsf
>   ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_POWER10),)
>   run-byte_reverse: QEMU_OPTS+=-cpu POWER10
>   run-plugin-byte_reverse-with-%: QEMU_OPTS+=-cpu POWER10
> diff --git a/tests/tcg/ppc64le/Makefile.target 
> b/tests/tcg/ppc64le/Makefile.target
> index 5e65b1590d..b8cd9bf73a 100644
> --- a/tests/tcg/ppc64le/Makefile.target
> +++ b/tests/tcg/ppc64le/Makefile.target
> @@ -10,6 +10,7 @@ endif
>   bcdsub: CFLAGS += -mpower8-vector
>   
>   PPC64LE_TESTS += byte_reverse
> +PPC64LE_TESTS += mtfsf
>   ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_POWER10),)
>   run-byte_reverse: QEMU_OPTS+=-cpu POWER10
>   run-plugin-byte_reverse-with-%: QEMU_OPTS+=-cpu POWER10
> diff --git a/tests/tcg/ppc64le/mtfsf.c b/tests/tcg/ppc64le/mtfsf.c
> new file mode 100644
> index 0000000000..b3d31f3637
> --- /dev/null
> +++ b/tests/tcg/ppc64le/mtfsf.c
> @@ -0,0 +1,61 @@
> +#include <stdlib.h>
> +#include <assert.h>
> +#include <signal.h>
> +#include <sys/prctl.h>
> +
> +#define FPSCR_VE     7  /* Floating-point invalid operation exception enable */
> +#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
> +#define FPSCR_FI     17 /* Floating-point fraction inexact                   */
> +
> +#define FP_VE           (1ull << FPSCR_VE)
> +#define FP_VXSOFT       (1ull << FPSCR_VXSOFT)
> +#define FP_FI           (1ull << FPSCR_FI)
> +
> +void sigfpe_handler(int sig, siginfo_t *si, void *ucontext)
> +{
> +    if (si->si_code == FPE_FLTINV) {
> +        exit(0);
> +    }
> +    exit(1);
> +}
> +
> +int main(void)
> +{
> +    union {
> +        double d;
> +        long long ll;
> +    } fpscr;
> +
> +    struct sigaction sa = {
> +        .sa_sigaction = sigfpe_handler,
> +        .sa_flags = SA_SIGINFO
> +    };
> +
> +    /*
> +     * Enable the MSR bits F0 and F1 to enable exceptions.
> +     * This shouldn't be needed in linux-user as these bits are enabled by
> +     * default, but this allows to execute either in a VM or a real machine
> +     * to compare the behaviors.
> +     */
> +    prctl(PR_SET_FPEXC, PR_FP_EXC_PRECISE);
> +
> +    /* First test if the FI bit is being set correctly */
> +    fpscr.ll = FP_FI;
> +    __builtin_mtfsf(0b11111111, fpscr.d);
> +    fpscr.d = __builtin_mffs();
> +    assert((fpscr.ll & FP_FI) != 0);
> +
> +    /* Then test if the deferred exception is being called correctly */
> +    sigaction(SIGFPE, &sa, NULL);
> +
> +    /*
> +     * Although the VXSOFT exception has been chosen, based on test in a Power9
> +     * any combination of exception bit + its enabling bit should work.
> +     * But if a different exception is chosen si_code check should
> +     * change accordingly.
> +     */
> +    fpscr.ll = FP_VE | FP_VXSOFT;
> +    __builtin_mtfsf(0b11111111, fpscr.d);
> +
> +    return 1;
> +}