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Re: [PATCH v8 09/10] target/ppc: PMU Event-Based exception support
From: |
David Gibson |
Subject: |
Re: [PATCH v8 09/10] target/ppc: PMU Event-Based exception support |
Date: |
Tue, 30 Nov 2021 15:15:47 +1100 |
On Thu, Nov 25, 2021 at 12:08:16PM -0300, Daniel Henrique Barboza wrote:
> From: Gustavo Romero <gromero@linux.ibm.com>
>
> Following up the rfebb implementation, this patch adds the EBB exception
> support that are triggered by Performance Monitor alerts. This exception
> occurs when an enabled PMU condition or event happens and both MMCR0_EBE
> and BESCR_PME are set.
>
> The supported PM alerts will consist of counter negative conditions of
> the PMU counters. This will be achieved by a timer mechanism that will
> predict when a counter becomes negative. The PMU timer callback will set
> the appropriate bits in MMCR0 and fire a PMC interrupt. The EBB
> exception code will then set the appropriate BESCR bits, set the next
> instruction pointer to the address pointed by the return register
> (SPR_EBBRR), and redirect execution to the handler (pointed by
> SPR_EBBHR).
>
> CC: Gustavo Romero <gustavo.romero@linaro.org>
> Signed-off-by: Gustavo Romero <gromero@linux.ibm.com>
> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> ---
> target/ppc/cpu.h | 5 ++++-
> target/ppc/excp_helper.c | 29 +++++++++++++++++++++++++++++
> target/ppc/power8-pmu.c | 35 +++++++++++++++++++++++++++++++++--
> 3 files changed, 66 insertions(+), 3 deletions(-)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index edb4488176..28ae904d76 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -129,8 +129,10 @@ enum {
> /* ISA 3.00 additions */
> POWERPC_EXCP_HVIRT = 101,
> POWERPC_EXCP_SYSCALL_VECTORED = 102, /* scv exception
> */
> + POWERPC_EXCP_EBB = 103, /* Event-based branch exception
> */
> +
> /* EOL
> */
> - POWERPC_EXCP_NB = 103,
> + POWERPC_EXCP_NB = 104,
> /* QEMU exceptions: special cases we want to stop translation
> */
> POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only
> */
> };
> @@ -2453,6 +2455,7 @@ enum {
> PPC_INTERRUPT_HMI, /* Hypervisor Maintenance interrupt */
> PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt */
> PPC_INTERRUPT_HVIRT, /* Hypervisor virtualization interrupt */
> + PPC_INTERRUPT_PMC, /* Hypervisor virtualization interrupt */
I'm guessing the comment here should be updated.
> };
>
> /* Processor Compatibility mask (PCR) */
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 7ead32279c..a26d266fe6 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -799,6 +799,23 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
> excp_model, int excp)
> cpu_abort(cs, "Non maskable external exception "
> "is not implemented yet !\n");
> break;
> + case POWERPC_EXCP_EBB: /* Event-based branch exception
> */
> + if ((env->spr[SPR_FSCR] & (1ull << FSCR_EBB)) &&
> + (env->spr[SPR_BESCR] & BESCR_GE) &&
> + (env->spr[SPR_BESCR] & BESCR_PME)) {
> + target_ulong nip;
> +
> + env->spr[SPR_BESCR] &= ~BESCR_GE; /* Clear GE */
> + env->spr[SPR_BESCR] |= BESCR_PMEO; /* Set PMEO */
> + env->spr[SPR_EBBRR] = env->nip; /* Save NIP for rfebb insn */
> + nip = env->spr[SPR_EBBHR]; /* EBB handler */
> + powerpc_set_excp_state(cpu, nip, env->msr);
> + }
> + /*
> + * This interrupt is handled by userspace. No need
> + * to proceed.
> + */
> + return;
> default:
> excp_invalid:
> cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
> @@ -1046,6 +1063,18 @@ static void ppc_hw_interrupt(CPUPPCState *env)
> powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_THERM);
> return;
> }
> + /* PMC -> Event-based branch exception */
> + if (env->pending_interrupts & (1 << PPC_INTERRUPT_PMC)) {
> + /*
> + * Performance Monitor event-based exception can only
> + * occur in problem state.
> + */
> + if (msr_pr == 1) {
> + env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PMC);
> + powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_EBB);
> + return;
> + }
> + }
> }
>
> if (env->resume_as_sreset) {
> diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
> index 98797f0b2f..330e0d2ae8 100644
> --- a/target/ppc/power8-pmu.c
> +++ b/target/ppc/power8-pmu.c
> @@ -290,6 +290,15 @@ void helper_store_pmc(CPUPPCState *env, uint32_t sprn,
> uint64_t value)
> pmc_update_overflow_timer(env, sprn);
> }
>
> +static void pmu_delete_timers(CPUPPCState *env)
> +{
> + int i;
> +
> + for (i = 0; i < PMU_TIMERS_NUM; i++) {
> + timer_del(env->pmu_cyc_overflow_timers[i]);
> + }
> +}
> +
> static void fire_PMC_interrupt(PowerPCCPU *cpu)
> {
> CPUPPCState *env = &cpu->env;
> @@ -298,8 +307,30 @@ static void fire_PMC_interrupt(PowerPCCPU *cpu)
> return;
> }
>
> - /* PMC interrupt not implemented yet */
> - return;
> + pmu_update_cycles(env);
> +
> + if (env->spr[SPR_POWER_MMCR0] & MMCR0_FCECE) {
> + env->spr[SPR_POWER_MMCR0] &= ~MMCR0_FCECE;
> + env->spr[SPR_POWER_MMCR0] |= MMCR0_FC;
> +
> + /* Changing MMCR0_FC demands a new hflags compute */
> + hreg_compute_hflags(env);
> +
> + /*
> + * Delete all pending timers if we need to freeze
> + * the PMC. We'll restart them when the PMC starts
> + * running again.
> + */
> + pmu_delete_timers(env);
> + }
> +
> + if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMAE) {
> + env->spr[SPR_POWER_MMCR0] &= ~MMCR0_PMAE;
> + env->spr[SPR_POWER_MMCR0] |= MMCR0_PMAO;
> + }
> +
> + /* Fire the PMC hardware exception */
> + ppc_set_irq(cpu, PPC_INTERRUPT_PMC, 1);
> }
>
> /* This helper assumes that the PMC is running. */
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- Re: [PATCH v8 04/10] target/ppc: PMU: update counters on MMCR1 write, (continued)
- [PATCH v8 05/10] target/ppc: enable PMU counter overflow with cycle events, Daniel Henrique Barboza, 2021/11/25
- [PATCH v8 06/10] target/ppc: enable PMU instruction count, Daniel Henrique Barboza, 2021/11/25
- [PATCH v8 07/10] target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event, Daniel Henrique Barboza, 2021/11/25
- [PATCH v8 08/10] PPC64/TCG: Implement 'rfebb' instruction, Daniel Henrique Barboza, 2021/11/25
- [PATCH v8 09/10] target/ppc: PMU Event-Based exception support, Daniel Henrique Barboza, 2021/11/25
- Re: [PATCH v8 09/10] target/ppc: PMU Event-Based exception support,
David Gibson <=
- [PATCH v8 10/10] target/ppc/excp_helper.c: EBB handling adjustments, Daniel Henrique Barboza, 2021/11/25