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[PULL 1/3] target/ppc: Fix register update on lf[sd]u[x]/stf[sd]u[x]
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From: |
Cédric Le Goater |
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Subject: |
[PULL 1/3] target/ppc: Fix register update on lf[sd]u[x]/stf[sd]u[x] |
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Date: |
Fri, 12 Nov 2021 12:15:41 +0100 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
These instructions should update the GPR indicated by the field RA
instead of RT. This error caused a regression on Mac OS 9 boot and some
graphical glitches in OS X.
Fixes: a39a106634a9 ("target/ppc: Move load and store floating point
instructions to decodetree")
Reported-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/translate/fp-impl.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/translate/fp-impl.c.inc
b/target/ppc/translate/fp-impl.c.inc
index d1dbb1b96b16..c9e05201d9e7 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -1328,7 +1328,7 @@ static bool do_lsfpsd(DisasContext *ctx, int rt, int ra,
TCGv displ,
set_fpr(rt, t0);
}
if (update) {
- tcg_gen_mov_tl(cpu_gpr[rt], ea);
+ tcg_gen_mov_tl(cpu_gpr[ra], ea);
}
tcg_temp_free_i64(t0);
tcg_temp_free(ea);
--
2.31.1