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[PATCH v3 25/25] target/ppc: cntlzdm/cnttzdm implementation without brco
From: |
matheus . ferst |
Subject: |
[PATCH v3 25/25] target/ppc: cntlzdm/cnttzdm implementation without brcond |
Date: |
Thu, 4 Nov 2021 09:37:19 -0300 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate/fixedpoint-impl.c.inc | 31 +++++++++++-----------
1 file changed, 16 insertions(+), 15 deletions(-)
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc
b/target/ppc/translate/fixedpoint-impl.c.inc
index e093562e2a..7fecff4579 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -416,32 +416,33 @@ static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
static void do_cntzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask, int64_t trail)
{
- TCGv_i64 tmp;
- TCGLabel *l1;
+ TCGv_i64 t0, t1;
- tmp = tcg_temp_local_new_i64();
- l1 = gen_new_label();
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
- tcg_gen_and_i64(tmp, src, mask);
+ tcg_gen_and_i64(t0, src, mask);
if (trail) {
- tcg_gen_ctzi_i64(tmp, tmp, 64);
+ tcg_gen_ctzi_i64(t0, t0, -1);
} else {
- tcg_gen_clzi_i64(tmp, tmp, 64);
+ tcg_gen_clzi_i64(t0, t0, -1);
}
- tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1);
-
- tcg_gen_subfi_i64(tmp, 64, tmp);
+ tcg_gen_setcondi_i64(TCG_COND_NE, t1, t0, -1);
+ tcg_gen_andi_i64(t0, t0, 63);
+ tcg_gen_xori_i64(t0, t0, 63);
if (trail) {
- tcg_gen_shl_i64(tmp, mask, tmp);
+ tcg_gen_shl_i64(t0, mask, t0);
+ tcg_gen_shl_i64(t0, t0, t1);
} else {
- tcg_gen_shr_i64(tmp, mask, tmp);
+ tcg_gen_shr_i64(t0, mask, t0);
+ tcg_gen_shr_i64(t0, t0, t1);
}
- tcg_gen_ctpop_i64(tmp, tmp);
- gen_set_label(l1);
+ tcg_gen_ctpop_i64(dst, t0);
- tcg_gen_mov_i64(dst, tmp);
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
}
static bool trans_CNTLZDM(DisasContext *ctx, arg_X *a)
--
2.25.1
- [PATCH v3 14/25] target/ppc: added the instructions LXVP and STXVP, (continued)
- [PATCH v3 14/25] target/ppc: added the instructions LXVP and STXVP, matheus . ferst, 2021/11/04
- [PATCH v3 16/25] target/ppc: added the instructions PLXV and PSTXV, matheus . ferst, 2021/11/04
- [PATCH v3 17/25] target/ppc: added the instructions PLXVP and PSTXVP, matheus . ferst, 2021/11/04
- [PATCH v3 19/25] target/ppc: moved XXSPLTIB to using decodetree, matheus . ferst, 2021/11/04
- [PATCH v3 18/25] target/ppc: moved XXSPLTW to using decodetree, matheus . ferst, 2021/11/04
- [PATCH v3 20/25] target/ppc: implemented XXSPLTI32DX, matheus . ferst, 2021/11/04
- [PATCH v3 21/25] target/ppc: Implemented XXSPLTIW using decodetree, matheus . ferst, 2021/11/04
- [PATCH v3 22/25] target/ppc: implemented XXSPLTIDP instruction, matheus . ferst, 2021/11/04
- [PATCH v3 23/25] target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions, matheus . ferst, 2021/11/04
- [PATCH v3 24/25] target/ppc: Implement lxvkq instruction, matheus . ferst, 2021/11/04
- [PATCH v3 25/25] target/ppc: cntlzdm/cnttzdm implementation without brcond,
matheus . ferst <=
- Re: [PATCH v3 00/25] PowerISA v3.1 instruction batch, David Gibson, 2021/11/04