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[PATCH v3 16/25] target/ppc: added the instructions PLXV and PSTXV
From: |
matheus . ferst |
Subject: |
[PATCH v3 16/25] target/ppc: added the instructions PLXV and PSTXV |
Date: |
Thu, 4 Nov 2021 09:37:10 -0300 |
From: "Lucas Mateus Castro (alqotel)" <lucas.castro@eldorado.org.br>
Implemented the instructions plxv and pstxv using decodetree
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.castro@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn64.decode | 10 ++++++++++
target/ppc/translate/vsx-impl.c.inc | 16 ++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 48756cd4ca..093439b370 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -23,6 +23,9 @@
@PLS_D ...... .. ... r:1 .. .................. \
...... rt:5 ra:5 ................ \
&PLS_D si=%pls_si
+@8LS_D_TSX ...... .. . .. r:1 .. .................. \
+ ..... rt:6 ra:5 ................ \
+ &PLS_D si=%pls_si
### Fixed-Point Load Instructions
@@ -137,3 +140,10 @@ PSTFD 000001 10 0--.-- .................. \
PNOP ................................ \
-------------------------------- @PNOP
}
+
+### VSX instructions
+
+PLXV 000001 00 0--.-- .................. \
+ 11001 ...... ..... ................ @8LS_D_TSX
+PSTXV 000001 00 0--.-- .................. \
+ 11011 ...... ..... ................ @8LS_D_TSX
diff --git a/target/ppc/translate/vsx-impl.c.inc
b/target/ppc/translate/vsx-impl.c.inc
index c66505ac71..1972127a22 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2019,6 +2019,20 @@ static bool do_lstxv_D(DisasContext *ctx, arg_D *a, bool
store, bool paired)
return do_lstxv(ctx, a->ra, tcg_constant_tl(a->si), a->rt, store, paired);
}
+static bool do_lstxv_PLS_D(DisasContext *ctx, arg_PLS_D *a,
+ bool store, bool paired)
+{
+ arg_D d;
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+
+ if (!resolve_PLS_D(ctx, &d, a)) {
+ return true;
+ }
+
+ return do_lstxv(ctx, d.ra, tcg_constant_tl(d.si), d.rt, store, paired);
+}
+
static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store, bool paired)
{
if (paired) {
@@ -2044,6 +2058,8 @@ TRANS(STXVX, do_lstxv_X, true, false)
TRANS(LXVX, do_lstxv_X, false, false)
TRANS(STXVPX, do_lstxv_X, true, true)
TRANS(LXVPX, do_lstxv_X, false, true)
+TRANS64(PSTXV, do_lstxv_PLS_D, true, false)
+TRANS64(PLXV, do_lstxv_PLS_D, false, false)
#undef GEN_XX2FORM
#undef GEN_XX3FORM
--
2.25.1
- [PATCH v3 07/25] target/ppc: Implement Vector Insert from VSR using GPR index insns, (continued)
- [PATCH v3 07/25] target/ppc: Implement Vector Insert from VSR using GPR index insns, matheus . ferst, 2021/11/04
- [PATCH v3 06/25] target/ppc: Implement Vector Insert Word from GPR using Immediate insns, matheus . ferst, 2021/11/04
- [PATCH v3 09/25] target/ppc: Implement Vector Extract Double to VSR using GPR index insns, matheus . ferst, 2021/11/04
- [PATCH v3 10/25] target/ppc: Introduce REQUIRE_VSX macro, matheus . ferst, 2021/11/04
- [PATCH v3 08/25] target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree, matheus . ferst, 2021/11/04
- [PATCH v3 11/25] target/ppc: receive high/low as argument in get/set_cpu_vsr, matheus . ferst, 2021/11/04
- [PATCH v3 12/25] target/ppc: moved stxv and lxv from legacy to decodtree, matheus . ferst, 2021/11/04
- [PATCH v3 13/25] target/ppc: moved stxvx and lxvx from legacy to decodtree, matheus . ferst, 2021/11/04
- [PATCH v3 15/25] target/ppc: added the instructions LXVPX and STXVPX, matheus . ferst, 2021/11/04
- [PATCH v3 14/25] target/ppc: added the instructions LXVP and STXVP, matheus . ferst, 2021/11/04
- [PATCH v3 16/25] target/ppc: added the instructions PLXV and PSTXV,
matheus . ferst <=
- [PATCH v3 17/25] target/ppc: added the instructions PLXVP and PSTXVP, matheus . ferst, 2021/11/04
- [PATCH v3 19/25] target/ppc: moved XXSPLTIB to using decodetree, matheus . ferst, 2021/11/04
- [PATCH v3 18/25] target/ppc: moved XXSPLTW to using decodetree, matheus . ferst, 2021/11/04
- [PATCH v3 20/25] target/ppc: implemented XXSPLTI32DX, matheus . ferst, 2021/11/04
- [PATCH v3 21/25] target/ppc: Implemented XXSPLTIW using decodetree, matheus . ferst, 2021/11/04
- [PATCH v3 22/25] target/ppc: implemented XXSPLTIDP instruction, matheus . ferst, 2021/11/04
- [PATCH v3 23/25] target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions, matheus . ferst, 2021/11/04
- [PATCH v3 24/25] target/ppc: Implement lxvkq instruction, matheus . ferst, 2021/11/04
- [PATCH v3 25/25] target/ppc: cntlzdm/cnttzdm implementation without brcond, matheus . ferst, 2021/11/04