[PATCH v3 00/25] PowerISA v3.1 instruction batch

[matheus . ferst]

From: Matheus Ferst <matheus.ferst@eldorado.org.br>

This patch series implements 56 new instructions for POWER10, moving 28
"old" instructions to decodetree along the way. The series is divided by
facility as follows:

- From patch 1 to 9: Vector
- From patch 10 to 24: Vector-Scalar Extensions
- From patch 25: Fixed-Point

Based-on: ppc-for-6.2

Patches without review: 5, 25

v3:
- Rebase on ppc-for-6.2
- Fixed endianness issue in vector insert helpers
- cntlzdm/cnttzdm implementation without brcond

v2:
- do_ea_calc now allocate and returns ea
- Inline version of cntlzdm/cnttzdm
- vecop_list removed from GVecGen* without fniv
- vsldbi/vsrdbi implemented with tcg_gen_extract2_i64
- memcpy instead of misaligned load/stores on vector insert instructions
- Simplified helper for Vector Extract
- Fixed [p]stxv[xp]/[p]lxv[xp] to always access to lowest address first
  in LE
- xxsplti32dx implemented with tcg_gen_st_i32
- valid_values mask removed from lxvkq implementation

Bruno Larsen (billionai) (6):
  target/ppc: Introduce REQUIRE_VSX macro
  target/ppc: moved XXSPLTW to using decodetree
  target/ppc: moved XXSPLTIB to using decodetree
  target/ppc: implemented XXSPLTI32DX
  target/ppc: Implemented XXSPLTIW using decodetree
  target/ppc: implemented XXSPLTIDP instruction

Lucas Mateus Castro (alqotel) (6):
  target/ppc: moved stxv and lxv from legacy to decodtree
  target/ppc: moved stxvx and lxvx from legacy to decodtree
  target/ppc: added the instructions LXVP and STXVP
  target/ppc: added the instructions LXVPX and STXVPX
  target/ppc: added the instructions PLXV and PSTXV
  target/ppc: added the instructions PLXVP and PSTXVP

Matheus Ferst (13):
  target/ppc: Move vcfuged to vmx-impl.c.inc
  target/ppc: Implement vclzdm/vctzdm instructions
  target/ppc: Implement vpdepd/vpextd instruction
  target/ppc: Implement vsldbi/vsrdbi instructions
  target/ppc: Implement Vector Insert from GPR using GPR index insns
  target/ppc: Implement Vector Insert Word from GPR using Immediate
    insns
  target/ppc: Implement Vector Insert from VSR using GPR index insns
  target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree
  target/ppc: Implement Vector Extract Double to VSR using GPR index
    insns
  target/ppc: receive high/low as argument in get/set_cpu_vsr
  target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd
    instructions
  target/ppc: Implement lxvkq instruction
  target/ppc: cntlzdm/cnttzdm implementation without brcond

 target/ppc/helper.h                        |  20 +-
 target/ppc/insn32.decode                   |  93 +++
 target/ppc/insn64.decode                   |  57 ++
 target/ppc/int_helper.c                    | 101 ++-
 target/ppc/translate.c                     |  26 +-
 target/ppc/translate/fixedpoint-impl.c.inc |  37 +-
 target/ppc/translate/vector-impl.c.inc     |  48 --
 target/ppc/translate/vmx-impl.c.inc        | 334 +++++++++-
 target/ppc/translate/vmx-ops.c.inc         |  10 +-
 target/ppc/translate/vsx-impl.c.inc        | 704 ++++++++++++---------
 target/ppc/translate/vsx-ops.c.inc         |   4 -
 11 files changed, 1006 insertions(+), 428 deletions(-)
 delete mode 100644 target/ppc/translate/vector-impl.c.inc

-- 
2.25.1