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[PATCH 08/33] target/ppc: Implement cnttzdm
From: |
matheus . ferst |
Subject: |
[PATCH 08/33] target/ppc: Implement cnttzdm |
Date: |
Thu, 21 Oct 2021 16:45:22 -0300 |
From: Luis Pires <luis.pires@eldorado.org.br>
Implement the following PowerISA v3.1 instruction:
cnttzdm: Count Trailing Zeros Doubleword Under Bit Mask
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/helper.h | 1 +
target/ppc/insn32.decode | 1 +
target/ppc/int_helper.c | 16 ++++++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 12 ++++++++++++
4 files changed, 30 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index ee7c82fb60..115bdf474a 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -48,6 +48,7 @@ DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_3(sraw, tl, env, tl, tl)
DEF_HELPER_FLAGS_2(cfuged, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(CNTLZDM, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(CNTTZDM, TCG_CALL_NO_RWG_SE, i64, i64, i64)
#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_2(cmpeqb, TCG_CALL_NO_RWG_SE, i32, tl, tl)
DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 221cb00dd6..3d692e9e6a 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -204,6 +204,7 @@ ADDPCIS 010011 ..... ..... .......... 00010 . @DX
CFUGED 011111 ..... ..... ..... 0011011100 - @X
CNTLZDM 011111 ..... ..... ..... 0000111011 - @X
+CNTTZDM 011111 ..... ..... ..... 1000111011 - @X
### Float-Point Load Instructions
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index dcef356034..efda78ed8e 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -404,6 +404,22 @@ uint64_t helper_CNTLZDM(uint64_t src, uint64_t mask)
return count;
}
+uint64_t helper_CNTTZDM(uint64_t src, uint64_t mask)
+{
+ uint64_t count = 0;
+
+ while (mask != 0) {
+ if ((src >> ctz64(mask)) & 1) {
+ break;
+ }
+
+ count++;
+ mask &= mask - 1;
+ }
+
+ return count;
+}
+
/*****************************************************************************/
/* PowerPC 601 specific instructions (POWER bridge) */
target_ulong helper_div(CPUPPCState *env, target_ulong arg1, target_ulong arg2)
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc
b/target/ppc/translate/fixedpoint-impl.c.inc
index 814fef2782..8c66fca96a 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -427,3 +427,15 @@ static bool trans_CNTLZDM(DisasContext *ctx, arg_X *a)
#endif
return true;
}
+
+static bool trans_CNTTZDM(DisasContext *ctx, arg_X *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+#if defined(TARGET_PPC64)
+ gen_helper_CNTTZDM(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
--
2.25.1
- Re: [PATCH 03/33] target/ppc: Move load and store floating point instructions to decodetree, (continued)
- [PATCH 04/33] target/ppc: Implement PLFS, PLFD, PSTFS and PSTFD instructions, matheus . ferst, 2021/10/21
- [PATCH 05/33] target/ppc: Move LQ and STQ to decodetree, matheus . ferst, 2021/10/21
- [PATCH 06/33] target/ppc: Implement PLQ and PSTQ, matheus . ferst, 2021/10/21
- [PATCH 07/33] target/ppc: Implement cntlzdm, matheus . ferst, 2021/10/21
- [PATCH 08/33] target/ppc: Implement cnttzdm,
matheus . ferst <=
- [PATCH 09/33] target/ppc: Implement pdepd instruction, matheus . ferst, 2021/10/21
- [PATCH 10/33] target/ppc: Implement pextd instruction, matheus . ferst, 2021/10/21
- [PATCH 11/33] target/ppc: Move vcfuged to vmx-impl.c.inc, matheus . ferst, 2021/10/21
- [PATCH 12/33] target/ppc: Implement vclzdm/vctzdm instructions, matheus . ferst, 2021/10/21
- [PATCH 13/33] target/ppc: Implement vpdepd/vpextd instruction, matheus . ferst, 2021/10/21