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Re: [PATCH 2/2] i2c/smbus_eeprom: Add feature bit to SPD data

From: BALATON Zoltan
Subject: Re: [PATCH 2/2] i2c/smbus_eeprom: Add feature bit to SPD data
Date: Sun, 18 Jul 2021 18:56:08 +0200 (CEST)

On Sun, 18 Jul 2021, David Gibson wrote:
On Thu, Jul 15, 2021 at 06:50:44PM +0200, BALATON Zoltan wrote:
Add the differential clock input feature bit to the generated SPD
data. Most guests don't seem to care but pegasos2 firmware version 1.2
checks for this bit and stops with unsupported module type error if
it's not present. Since this feature is likely present on real memory
modules add it in the general code rather than patching the generated
SPD data in pegasos2 board only.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
I've tested it with the firmware of pegasos2, sam460ex, fuloong2e and
g3beige (latter is not upstream yet) that are the only ones using this
function currently. Probably this could go in via PPC tree with my
other pegasos2 fix if respective maitainers ack this patch.

 hw/i2c/smbus_eeprom.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

This isn't really my area, so I'd need acks to take it through my

Since this is only used by fuloong2e apart from pegasos2 and sam460ex an ack from Philippe may be what's needed here. Technically it's in i2c because the SPD EEPROM is connected via i2c but other than that it has nothing to do with that so Corey is just included because a file in hw/i2c is changed so it could go in via any of you three. Since there's another pegasos2 related fix queued going via PPC tree would make sense I think.


diff --git a/hw/i2c/smbus_eeprom.c b/hw/i2c/smbus_eeprom.c
index 4d2bf99207..12c5741f38 100644
--- a/hw/i2c/smbus_eeprom.c
+++ b/hw/i2c/smbus_eeprom.c
@@ -276,7 +276,7 @@ uint8_t *spd_data_generate(enum sdram_type type, ram_addr_t 
     spd[18] = 12;   /* ~CAS latencies supported */
     spd[19] = (type == DDR2 ? 0 : 1); /* reserved / ~CS latencies supported */
     spd[20] = 2;    /* DIMM type / ~WE latencies */
-                    /* module features */
+    spd[21] = (type < DDR2 ? 0x20 : 0); /* module features */
                     /* memory chip features */
     spd[23] = 0x12; /* clock cycle time @ medium CAS latency */
                     /* data access time */

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